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7b77452ec5
The current delay implementation uses the yield instruction, which is a hint that it is beneficial to schedule another thread. As this is a hint, it may be implemented as a NOP, causing all delays to be busy loops. This is the case for many existing CPUs. Taking advantage of the generic timer sending periodic events to all cores, we can use WFE during delays to reduce power consumption. This is beneficial only for delays longer than the period of the timer event stream. If timer event stream is not enabled, delays will behave as yield/busy loops. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
120 lines
2.9 KiB
C
120 lines
2.9 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
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#define __CLKSOURCE_ARM_ARCH_TIMER_H
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#include <linux/bitops.h>
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#include <linux/timecounter.h>
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#include <linux/types.h>
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#define ARCH_TIMER_TYPE_CP15 BIT(0)
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#define ARCH_TIMER_TYPE_MEM BIT(1)
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
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#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
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#define CNTHCTL_EL1PCTEN (1 << 0)
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#define CNTHCTL_EL1PCEN (1 << 1)
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#define CNTHCTL_EVNTEN (1 << 2)
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#define CNTHCTL_EVNTDIR (1 << 3)
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#define CNTHCTL_EVNTI (0xF << 4)
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enum arch_timer_reg {
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ARCH_TIMER_REG_CTRL,
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ARCH_TIMER_REG_TVAL,
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};
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enum arch_timer_ppi_nr {
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ARCH_TIMER_PHYS_SECURE_PPI,
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ARCH_TIMER_PHYS_NONSECURE_PPI,
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ARCH_TIMER_VIRT_PPI,
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ARCH_TIMER_HYP_PPI,
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ARCH_TIMER_MAX_TIMER_PPI
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};
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enum arch_timer_spi_nr {
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ARCH_TIMER_PHYS_SPI,
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ARCH_TIMER_VIRT_SPI,
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ARCH_TIMER_MAX_TIMER_SPI
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};
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#define ARCH_TIMER_PHYS_ACCESS 0
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#define ARCH_TIMER_VIRT_ACCESS 1
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#define ARCH_TIMER_MEM_PHYS_ACCESS 2
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#define ARCH_TIMER_MEM_VIRT_ACCESS 3
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#define ARCH_TIMER_MEM_MAX_FRAMES 8
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#define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
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#define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
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#define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
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#define ARCH_TIMER_EVT_TRIGGER_SHIFT (4)
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#define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
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#define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
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#define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
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#define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
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#define ARCH_TIMER_EVT_STREAM_FREQ \
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(USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)
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struct arch_timer_kvm_info {
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struct timecounter timecounter;
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int virtual_irq;
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};
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struct arch_timer_mem_frame {
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bool valid;
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phys_addr_t cntbase;
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size_t size;
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int phys_irq;
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int virt_irq;
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};
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struct arch_timer_mem {
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phys_addr_t cntctlbase;
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size_t size;
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struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES];
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};
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#ifdef CONFIG_ARM_ARCH_TIMER
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extern u32 arch_timer_get_rate(void);
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extern u64 (*arch_timer_read_counter)(void);
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extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
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extern bool arch_timer_evtstrm_available(void);
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#else
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static inline u32 arch_timer_get_rate(void)
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{
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return 0;
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}
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static inline u64 arch_timer_read_counter(void)
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{
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return 0;
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}
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static inline bool arch_timer_evtstrm_available(void)
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{
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return false;
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}
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#endif
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#endif
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