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a4289dc2ec
The Linux kernel already has the concept of IRQ domain, wherein a component can expose a set of IRQs which are managed by a particular interrupt controller chip or other subsystem. The PCI driver exposes the notion of an IRQ domain for Message-Signaled Interrupts (MSI) from PCI Express devices. This patch exposes the functions which are necessary for creating a MSI IRQ domain within a module. [ tglx: Split it into x86 and core irq parts ] Signed-off-by: Jake Oshins <jakeo@microsoft.com> Cc: gregkh@linuxfoundation.org Cc: kys@microsoft.com Cc: devel@linuxdriverproject.org Cc: olaf@aepfle.de Cc: apw@canonical.com Cc: vkuznets@redhat.com Cc: haiyangz@microsoft.com Cc: marc.zyngier@arm.com Cc: bhelgaas@google.com Link: http://lkml.kernel.org/r/1449769983-12948-4-git-send-email-jakeo@microsoft.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
1092 lines
27 KiB
C
1092 lines
27 KiB
C
/*
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* linux/kernel/irq/chip.c
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*
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* Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
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* Copyright (C) 2005-2006, Thomas Gleixner, Russell King
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*
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* This file contains the core interrupt handling code, for irq-chip
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* based architectures.
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*
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* Detailed information is available in Documentation/DocBook/genericirq
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*/
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/irqdomain.h>
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#include <trace/events/irq.h>
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#include "internals.h"
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static irqreturn_t bad_chained_irq(int irq, void *dev_id)
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{
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WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
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return IRQ_NONE;
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}
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/*
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* Chained handlers should never call action on their IRQ. This default
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* action will emit warning if such thing happens.
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*/
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struct irqaction chained_action = {
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.handler = bad_chained_irq,
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};
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/**
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* irq_set_chip - set the irq chip for an irq
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* @irq: irq number
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* @chip: pointer to irq chip description structure
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*/
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int irq_set_chip(unsigned int irq, struct irq_chip *chip)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
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if (!desc)
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return -EINVAL;
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if (!chip)
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chip = &no_irq_chip;
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desc->irq_data.chip = chip;
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irq_put_desc_unlock(desc, flags);
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/*
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* For !CONFIG_SPARSE_IRQ make the irq show up in
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* allocated_irqs.
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*/
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irq_mark_irq(irq);
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return 0;
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}
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EXPORT_SYMBOL(irq_set_chip);
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/**
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* irq_set_type - set the irq trigger type for an irq
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* @irq: irq number
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* @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
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*/
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int irq_set_irq_type(unsigned int irq, unsigned int type)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
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int ret = 0;
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if (!desc)
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return -EINVAL;
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type &= IRQ_TYPE_SENSE_MASK;
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ret = __irq_set_trigger(desc, type);
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irq_put_desc_busunlock(desc, flags);
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return ret;
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}
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EXPORT_SYMBOL(irq_set_irq_type);
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/**
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* irq_set_handler_data - set irq handler data for an irq
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* @irq: Interrupt number
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* @data: Pointer to interrupt specific data
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*
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* Set the hardware irq controller data for an irq
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*/
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int irq_set_handler_data(unsigned int irq, void *data)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
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if (!desc)
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return -EINVAL;
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desc->irq_common_data.handler_data = data;
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irq_put_desc_unlock(desc, flags);
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return 0;
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}
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EXPORT_SYMBOL(irq_set_handler_data);
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/**
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* irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
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* @irq_base: Interrupt number base
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* @irq_offset: Interrupt number offset
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* @entry: Pointer to MSI descriptor data
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*
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* Set the MSI descriptor entry for an irq at offset
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*/
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int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
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struct msi_desc *entry)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
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if (!desc)
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return -EINVAL;
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desc->irq_common_data.msi_desc = entry;
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if (entry && !irq_offset)
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entry->irq = irq_base;
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irq_put_desc_unlock(desc, flags);
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return 0;
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}
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/**
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* irq_set_msi_desc - set MSI descriptor data for an irq
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* @irq: Interrupt number
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* @entry: Pointer to MSI descriptor data
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*
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* Set the MSI descriptor entry for an irq
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*/
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int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
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{
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return irq_set_msi_desc_off(irq, 0, entry);
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}
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/**
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* irq_set_chip_data - set irq chip data for an irq
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* @irq: Interrupt number
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* @data: Pointer to chip specific data
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*
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* Set the hardware irq chip data for an irq
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*/
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int irq_set_chip_data(unsigned int irq, void *data)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
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if (!desc)
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return -EINVAL;
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desc->irq_data.chip_data = data;
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irq_put_desc_unlock(desc, flags);
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return 0;
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}
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EXPORT_SYMBOL(irq_set_chip_data);
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struct irq_data *irq_get_irq_data(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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return desc ? &desc->irq_data : NULL;
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}
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EXPORT_SYMBOL_GPL(irq_get_irq_data);
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static void irq_state_clr_disabled(struct irq_desc *desc)
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{
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irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
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}
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static void irq_state_set_disabled(struct irq_desc *desc)
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{
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irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
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}
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static void irq_state_clr_masked(struct irq_desc *desc)
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{
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irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
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}
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static void irq_state_set_masked(struct irq_desc *desc)
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{
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irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
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}
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int irq_startup(struct irq_desc *desc, bool resend)
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{
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int ret = 0;
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irq_state_clr_disabled(desc);
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desc->depth = 0;
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irq_domain_activate_irq(&desc->irq_data);
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if (desc->irq_data.chip->irq_startup) {
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ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
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irq_state_clr_masked(desc);
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} else {
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irq_enable(desc);
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}
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if (resend)
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check_irq_resend(desc);
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return ret;
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}
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void irq_shutdown(struct irq_desc *desc)
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{
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irq_state_set_disabled(desc);
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desc->depth = 1;
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if (desc->irq_data.chip->irq_shutdown)
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desc->irq_data.chip->irq_shutdown(&desc->irq_data);
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else if (desc->irq_data.chip->irq_disable)
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desc->irq_data.chip->irq_disable(&desc->irq_data);
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else
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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irq_domain_deactivate_irq(&desc->irq_data);
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irq_state_set_masked(desc);
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}
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void irq_enable(struct irq_desc *desc)
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{
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irq_state_clr_disabled(desc);
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if (desc->irq_data.chip->irq_enable)
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desc->irq_data.chip->irq_enable(&desc->irq_data);
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else
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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irq_state_clr_masked(desc);
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}
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/**
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* irq_disable - Mark interrupt disabled
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* @desc: irq descriptor which should be disabled
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*
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* If the chip does not implement the irq_disable callback, we
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* use a lazy disable approach. That means we mark the interrupt
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* disabled, but leave the hardware unmasked. That's an
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* optimization because we avoid the hardware access for the
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* common case where no interrupt happens after we marked it
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* disabled. If an interrupt happens, then the interrupt flow
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* handler masks the line at the hardware level and marks it
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* pending.
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*
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* If the interrupt chip does not implement the irq_disable callback,
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* a driver can disable the lazy approach for a particular irq line by
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* calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
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* be used for devices which cannot disable the interrupt at the
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* device level under certain circumstances and have to use
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* disable_irq[_nosync] instead.
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*/
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void irq_disable(struct irq_desc *desc)
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{
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irq_state_set_disabled(desc);
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if (desc->irq_data.chip->irq_disable) {
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desc->irq_data.chip->irq_disable(&desc->irq_data);
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irq_state_set_masked(desc);
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} else if (irq_settings_disable_unlazy(desc)) {
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mask_irq(desc);
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}
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}
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void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
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{
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if (desc->irq_data.chip->irq_enable)
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desc->irq_data.chip->irq_enable(&desc->irq_data);
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else
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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cpumask_set_cpu(cpu, desc->percpu_enabled);
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}
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void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
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{
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if (desc->irq_data.chip->irq_disable)
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desc->irq_data.chip->irq_disable(&desc->irq_data);
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else
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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cpumask_clear_cpu(cpu, desc->percpu_enabled);
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}
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static inline void mask_ack_irq(struct irq_desc *desc)
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{
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if (desc->irq_data.chip->irq_mask_ack)
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desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
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else {
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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if (desc->irq_data.chip->irq_ack)
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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}
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irq_state_set_masked(desc);
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}
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void mask_irq(struct irq_desc *desc)
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{
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if (desc->irq_data.chip->irq_mask) {
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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irq_state_set_masked(desc);
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}
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}
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void unmask_irq(struct irq_desc *desc)
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{
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if (desc->irq_data.chip->irq_unmask) {
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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irq_state_clr_masked(desc);
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}
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}
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void unmask_threaded_irq(struct irq_desc *desc)
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{
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struct irq_chip *chip = desc->irq_data.chip;
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if (chip->flags & IRQCHIP_EOI_THREADED)
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chip->irq_eoi(&desc->irq_data);
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if (chip->irq_unmask) {
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chip->irq_unmask(&desc->irq_data);
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irq_state_clr_masked(desc);
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}
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}
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/*
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* handle_nested_irq - Handle a nested irq from a irq thread
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* @irq: the interrupt number
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*
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* Handle interrupts which are nested into a threaded interrupt
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* handler. The handler function is called inside the calling
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* threads context.
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*/
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void handle_nested_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irqaction *action;
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irqreturn_t action_ret;
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might_sleep();
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raw_spin_lock_irq(&desc->lock);
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desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
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action = desc->action;
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if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
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desc->istate |= IRQS_PENDING;
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goto out_unlock;
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}
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kstat_incr_irqs_this_cpu(desc);
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irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
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raw_spin_unlock_irq(&desc->lock);
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action_ret = action->thread_fn(action->irq, action->dev_id);
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if (!noirqdebug)
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note_interrupt(desc, action_ret);
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raw_spin_lock_irq(&desc->lock);
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irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
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out_unlock:
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raw_spin_unlock_irq(&desc->lock);
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}
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EXPORT_SYMBOL_GPL(handle_nested_irq);
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static bool irq_check_poll(struct irq_desc *desc)
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{
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if (!(desc->istate & IRQS_POLL_INPROGRESS))
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return false;
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return irq_wait_for_poll(desc);
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}
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static bool irq_may_run(struct irq_desc *desc)
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{
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unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
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/*
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* If the interrupt is not in progress and is not an armed
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* wakeup interrupt, proceed.
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*/
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if (!irqd_has_set(&desc->irq_data, mask))
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return true;
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/*
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* If the interrupt is an armed wakeup source, mark it pending
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* and suspended, disable it and notify the pm core about the
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* event.
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*/
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if (irq_pm_check_wakeup(desc))
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return false;
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/*
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* Handle a potential concurrent poll on a different core.
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*/
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return irq_check_poll(desc);
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}
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|
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/**
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* handle_simple_irq - Simple and software-decoded IRQs.
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* @desc: the interrupt description structure for this irq
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*
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* Simple interrupts are either sent from a demultiplexing interrupt
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* handler or come from hardware, where no interrupt hardware control
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* is necessary.
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*
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* Note: The caller is expected to handle the ack, clear, mask and
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* unmask issues if necessary.
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*/
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void handle_simple_irq(struct irq_desc *desc)
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{
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raw_spin_lock(&desc->lock);
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if (!irq_may_run(desc))
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goto out_unlock;
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desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
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if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
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desc->istate |= IRQS_PENDING;
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goto out_unlock;
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}
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kstat_incr_irqs_this_cpu(desc);
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handle_irq_event(desc);
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out_unlock:
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raw_spin_unlock(&desc->lock);
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}
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EXPORT_SYMBOL_GPL(handle_simple_irq);
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|
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/*
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* Called unconditionally from handle_level_irq() and only for oneshot
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* interrupts from handle_fasteoi_irq()
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*/
|
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static void cond_unmask_irq(struct irq_desc *desc)
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{
|
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/*
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* We need to unmask in the following cases:
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* - Standard level irq (IRQF_ONESHOT is not set)
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* - Oneshot irq which did not wake the thread (caused by a
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* spurious interrupt or a primary handler handling it
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* completely).
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*/
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if (!irqd_irq_disabled(&desc->irq_data) &&
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irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
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unmask_irq(desc);
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}
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|
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/**
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* handle_level_irq - Level type irq handler
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* @desc: the interrupt description structure for this irq
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*
|
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* Level type interrupts are active as long as the hardware line has
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* the active level. This may require to mask the interrupt and unmask
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* it after the associated handler has acknowledged the device, so the
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* interrupt line is back to inactive.
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*/
|
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void handle_level_irq(struct irq_desc *desc)
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{
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raw_spin_lock(&desc->lock);
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mask_ack_irq(desc);
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|
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if (!irq_may_run(desc))
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goto out_unlock;
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|
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desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
|
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|
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/*
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* If its disabled or no action available
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* keep it masked and get out of here
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*/
|
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if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
|
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desc->istate |= IRQS_PENDING;
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goto out_unlock;
|
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}
|
|
|
|
kstat_incr_irqs_this_cpu(desc);
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handle_irq_event(desc);
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|
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cond_unmask_irq(desc);
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|
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out_unlock:
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raw_spin_unlock(&desc->lock);
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}
|
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EXPORT_SYMBOL_GPL(handle_level_irq);
|
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|
|
#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
|
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static inline void preflow_handler(struct irq_desc *desc)
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{
|
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if (desc->preflow_handler)
|
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desc->preflow_handler(&desc->irq_data);
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}
|
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#else
|
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static inline void preflow_handler(struct irq_desc *desc) { }
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#endif
|
|
|
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static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
|
|
{
|
|
if (!(desc->istate & IRQS_ONESHOT)) {
|
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chip->irq_eoi(&desc->irq_data);
|
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return;
|
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}
|
|
/*
|
|
* We need to unmask in the following cases:
|
|
* - Oneshot irq which did not wake the thread (caused by a
|
|
* spurious interrupt or a primary handler handling it
|
|
* completely).
|
|
*/
|
|
if (!irqd_irq_disabled(&desc->irq_data) &&
|
|
irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
|
|
chip->irq_eoi(&desc->irq_data);
|
|
unmask_irq(desc);
|
|
} else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
|
|
chip->irq_eoi(&desc->irq_data);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* handle_fasteoi_irq - irq handler for transparent controllers
|
|
* @desc: the interrupt description structure for this irq
|
|
*
|
|
* Only a single callback will be issued to the chip: an ->eoi()
|
|
* call when the interrupt has been serviced. This enables support
|
|
* for modern forms of interrupt handlers, which handle the flow
|
|
* details in hardware, transparently.
|
|
*/
|
|
void handle_fasteoi_irq(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = desc->irq_data.chip;
|
|
|
|
raw_spin_lock(&desc->lock);
|
|
|
|
if (!irq_may_run(desc))
|
|
goto out;
|
|
|
|
desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
|
|
|
|
/*
|
|
* If its disabled or no action available
|
|
* then mask it and get out of here:
|
|
*/
|
|
if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
|
|
desc->istate |= IRQS_PENDING;
|
|
mask_irq(desc);
|
|
goto out;
|
|
}
|
|
|
|
kstat_incr_irqs_this_cpu(desc);
|
|
if (desc->istate & IRQS_ONESHOT)
|
|
mask_irq(desc);
|
|
|
|
preflow_handler(desc);
|
|
handle_irq_event(desc);
|
|
|
|
cond_unmask_eoi_irq(desc, chip);
|
|
|
|
raw_spin_unlock(&desc->lock);
|
|
return;
|
|
out:
|
|
if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
|
|
chip->irq_eoi(&desc->irq_data);
|
|
raw_spin_unlock(&desc->lock);
|
|
}
|
|
EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
|
|
|
|
/**
|
|
* handle_edge_irq - edge type IRQ handler
|
|
* @desc: the interrupt description structure for this irq
|
|
*
|
|
* Interrupt occures on the falling and/or rising edge of a hardware
|
|
* signal. The occurrence is latched into the irq controller hardware
|
|
* and must be acked in order to be reenabled. After the ack another
|
|
* interrupt can happen on the same source even before the first one
|
|
* is handled by the associated event handler. If this happens it
|
|
* might be necessary to disable (mask) the interrupt depending on the
|
|
* controller hardware. This requires to reenable the interrupt inside
|
|
* of the loop which handles the interrupts which have arrived while
|
|
* the handler was running. If all pending interrupts are handled, the
|
|
* loop is left.
|
|
*/
|
|
void handle_edge_irq(struct irq_desc *desc)
|
|
{
|
|
raw_spin_lock(&desc->lock);
|
|
|
|
desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
|
|
|
|
if (!irq_may_run(desc)) {
|
|
desc->istate |= IRQS_PENDING;
|
|
mask_ack_irq(desc);
|
|
goto out_unlock;
|
|
}
|
|
|
|
/*
|
|
* If its disabled or no action available then mask it and get
|
|
* out of here.
|
|
*/
|
|
if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
|
|
desc->istate |= IRQS_PENDING;
|
|
mask_ack_irq(desc);
|
|
goto out_unlock;
|
|
}
|
|
|
|
kstat_incr_irqs_this_cpu(desc);
|
|
|
|
/* Start handling the irq */
|
|
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
|
|
|
do {
|
|
if (unlikely(!desc->action)) {
|
|
mask_irq(desc);
|
|
goto out_unlock;
|
|
}
|
|
|
|
/*
|
|
* When another irq arrived while we were handling
|
|
* one, we could have masked the irq.
|
|
* Renable it, if it was not disabled in meantime.
|
|
*/
|
|
if (unlikely(desc->istate & IRQS_PENDING)) {
|
|
if (!irqd_irq_disabled(&desc->irq_data) &&
|
|
irqd_irq_masked(&desc->irq_data))
|
|
unmask_irq(desc);
|
|
}
|
|
|
|
handle_irq_event(desc);
|
|
|
|
} while ((desc->istate & IRQS_PENDING) &&
|
|
!irqd_irq_disabled(&desc->irq_data));
|
|
|
|
out_unlock:
|
|
raw_spin_unlock(&desc->lock);
|
|
}
|
|
EXPORT_SYMBOL(handle_edge_irq);
|
|
|
|
#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
|
|
/**
|
|
* handle_edge_eoi_irq - edge eoi type IRQ handler
|
|
* @desc: the interrupt description structure for this irq
|
|
*
|
|
* Similar as the above handle_edge_irq, but using eoi and w/o the
|
|
* mask/unmask logic.
|
|
*/
|
|
void handle_edge_eoi_irq(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
|
|
raw_spin_lock(&desc->lock);
|
|
|
|
desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
|
|
|
|
if (!irq_may_run(desc)) {
|
|
desc->istate |= IRQS_PENDING;
|
|
goto out_eoi;
|
|
}
|
|
|
|
/*
|
|
* If its disabled or no action available then mask it and get
|
|
* out of here.
|
|
*/
|
|
if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
|
|
desc->istate |= IRQS_PENDING;
|
|
goto out_eoi;
|
|
}
|
|
|
|
kstat_incr_irqs_this_cpu(desc);
|
|
|
|
do {
|
|
if (unlikely(!desc->action))
|
|
goto out_eoi;
|
|
|
|
handle_irq_event(desc);
|
|
|
|
} while ((desc->istate & IRQS_PENDING) &&
|
|
!irqd_irq_disabled(&desc->irq_data));
|
|
|
|
out_eoi:
|
|
chip->irq_eoi(&desc->irq_data);
|
|
raw_spin_unlock(&desc->lock);
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* handle_percpu_irq - Per CPU local irq handler
|
|
* @desc: the interrupt description structure for this irq
|
|
*
|
|
* Per CPU interrupts on SMP machines without locking requirements
|
|
*/
|
|
void handle_percpu_irq(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
|
|
kstat_incr_irqs_this_cpu(desc);
|
|
|
|
if (chip->irq_ack)
|
|
chip->irq_ack(&desc->irq_data);
|
|
|
|
handle_irq_event_percpu(desc);
|
|
|
|
if (chip->irq_eoi)
|
|
chip->irq_eoi(&desc->irq_data);
|
|
}
|
|
|
|
/**
|
|
* handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
|
|
* @desc: the interrupt description structure for this irq
|
|
*
|
|
* Per CPU interrupts on SMP machines without locking requirements. Same as
|
|
* handle_percpu_irq() above but with the following extras:
|
|
*
|
|
* action->percpu_dev_id is a pointer to percpu variables which
|
|
* contain the real device id for the cpu on which this handler is
|
|
* called
|
|
*/
|
|
void handle_percpu_devid_irq(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct irqaction *action = desc->action;
|
|
void *dev_id = raw_cpu_ptr(action->percpu_dev_id);
|
|
unsigned int irq = irq_desc_get_irq(desc);
|
|
irqreturn_t res;
|
|
|
|
kstat_incr_irqs_this_cpu(desc);
|
|
|
|
if (chip->irq_ack)
|
|
chip->irq_ack(&desc->irq_data);
|
|
|
|
trace_irq_handler_entry(irq, action);
|
|
res = action->handler(irq, dev_id);
|
|
trace_irq_handler_exit(irq, action, res);
|
|
|
|
if (chip->irq_eoi)
|
|
chip->irq_eoi(&desc->irq_data);
|
|
}
|
|
|
|
void
|
|
__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
|
|
int is_chained, const char *name)
|
|
{
|
|
if (!handle) {
|
|
handle = handle_bad_irq;
|
|
} else {
|
|
struct irq_data *irq_data = &desc->irq_data;
|
|
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
|
/*
|
|
* With hierarchical domains we might run into a
|
|
* situation where the outermost chip is not yet set
|
|
* up, but the inner chips are there. Instead of
|
|
* bailing we install the handler, but obviously we
|
|
* cannot enable/startup the interrupt at this point.
|
|
*/
|
|
while (irq_data) {
|
|
if (irq_data->chip != &no_irq_chip)
|
|
break;
|
|
/*
|
|
* Bail out if the outer chip is not set up
|
|
* and the interrrupt supposed to be started
|
|
* right away.
|
|
*/
|
|
if (WARN_ON(is_chained))
|
|
return;
|
|
/* Try the parent */
|
|
irq_data = irq_data->parent_data;
|
|
}
|
|
#endif
|
|
if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
|
|
return;
|
|
}
|
|
|
|
/* Uninstall? */
|
|
if (handle == handle_bad_irq) {
|
|
if (desc->irq_data.chip != &no_irq_chip)
|
|
mask_ack_irq(desc);
|
|
irq_state_set_disabled(desc);
|
|
if (is_chained)
|
|
desc->action = NULL;
|
|
desc->depth = 1;
|
|
}
|
|
desc->handle_irq = handle;
|
|
desc->name = name;
|
|
|
|
if (handle != handle_bad_irq && is_chained) {
|
|
irq_settings_set_noprobe(desc);
|
|
irq_settings_set_norequest(desc);
|
|
irq_settings_set_nothread(desc);
|
|
desc->action = &chained_action;
|
|
irq_startup(desc, true);
|
|
}
|
|
}
|
|
|
|
void
|
|
__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
|
|
const char *name)
|
|
{
|
|
unsigned long flags;
|
|
struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
|
|
|
|
if (!desc)
|
|
return;
|
|
|
|
__irq_do_set_handler(desc, handle, is_chained, name);
|
|
irq_put_desc_busunlock(desc, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(__irq_set_handler);
|
|
|
|
void
|
|
irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
|
|
void *data)
|
|
{
|
|
unsigned long flags;
|
|
struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
|
|
|
|
if (!desc)
|
|
return;
|
|
|
|
__irq_do_set_handler(desc, handle, 1, NULL);
|
|
desc->irq_common_data.handler_data = data;
|
|
|
|
irq_put_desc_busunlock(desc, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
|
|
|
|
void
|
|
irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
|
|
irq_flow_handler_t handle, const char *name)
|
|
{
|
|
irq_set_chip(irq, chip);
|
|
__irq_set_handler(irq, handle, 0, name);
|
|
}
|
|
EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
|
|
|
|
void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
|
|
{
|
|
unsigned long flags;
|
|
struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
|
|
|
|
if (!desc)
|
|
return;
|
|
irq_settings_clr_and_set(desc, clr, set);
|
|
|
|
irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
|
|
IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
|
|
if (irq_settings_has_no_balance_set(desc))
|
|
irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
|
|
if (irq_settings_is_per_cpu(desc))
|
|
irqd_set(&desc->irq_data, IRQD_PER_CPU);
|
|
if (irq_settings_can_move_pcntxt(desc))
|
|
irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
|
|
if (irq_settings_is_level(desc))
|
|
irqd_set(&desc->irq_data, IRQD_LEVEL);
|
|
|
|
irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
|
|
|
|
irq_put_desc_unlock(desc, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(irq_modify_status);
|
|
|
|
/**
|
|
* irq_cpu_online - Invoke all irq_cpu_online functions.
|
|
*
|
|
* Iterate through all irqs and invoke the chip.irq_cpu_online()
|
|
* for each.
|
|
*/
|
|
void irq_cpu_online(void)
|
|
{
|
|
struct irq_desc *desc;
|
|
struct irq_chip *chip;
|
|
unsigned long flags;
|
|
unsigned int irq;
|
|
|
|
for_each_active_irq(irq) {
|
|
desc = irq_to_desc(irq);
|
|
if (!desc)
|
|
continue;
|
|
|
|
raw_spin_lock_irqsave(&desc->lock, flags);
|
|
|
|
chip = irq_data_get_irq_chip(&desc->irq_data);
|
|
if (chip && chip->irq_cpu_online &&
|
|
(!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
|
|
!irqd_irq_disabled(&desc->irq_data)))
|
|
chip->irq_cpu_online(&desc->irq_data);
|
|
|
|
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* irq_cpu_offline - Invoke all irq_cpu_offline functions.
|
|
*
|
|
* Iterate through all irqs and invoke the chip.irq_cpu_offline()
|
|
* for each.
|
|
*/
|
|
void irq_cpu_offline(void)
|
|
{
|
|
struct irq_desc *desc;
|
|
struct irq_chip *chip;
|
|
unsigned long flags;
|
|
unsigned int irq;
|
|
|
|
for_each_active_irq(irq) {
|
|
desc = irq_to_desc(irq);
|
|
if (!desc)
|
|
continue;
|
|
|
|
raw_spin_lock_irqsave(&desc->lock, flags);
|
|
|
|
chip = irq_data_get_irq_chip(&desc->irq_data);
|
|
if (chip && chip->irq_cpu_offline &&
|
|
(!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
|
|
!irqd_irq_disabled(&desc->irq_data)))
|
|
chip->irq_cpu_offline(&desc->irq_data);
|
|
|
|
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
|
/**
|
|
* irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
|
|
* NULL)
|
|
* @data: Pointer to interrupt specific data
|
|
*/
|
|
void irq_chip_enable_parent(struct irq_data *data)
|
|
{
|
|
data = data->parent_data;
|
|
if (data->chip->irq_enable)
|
|
data->chip->irq_enable(data);
|
|
else
|
|
data->chip->irq_unmask(data);
|
|
}
|
|
|
|
/**
|
|
* irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
|
|
* NULL)
|
|
* @data: Pointer to interrupt specific data
|
|
*/
|
|
void irq_chip_disable_parent(struct irq_data *data)
|
|
{
|
|
data = data->parent_data;
|
|
if (data->chip->irq_disable)
|
|
data->chip->irq_disable(data);
|
|
else
|
|
data->chip->irq_mask(data);
|
|
}
|
|
|
|
/**
|
|
* irq_chip_ack_parent - Acknowledge the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
*/
|
|
void irq_chip_ack_parent(struct irq_data *data)
|
|
{
|
|
data = data->parent_data;
|
|
data->chip->irq_ack(data);
|
|
}
|
|
EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
|
|
|
|
/**
|
|
* irq_chip_mask_parent - Mask the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
*/
|
|
void irq_chip_mask_parent(struct irq_data *data)
|
|
{
|
|
data = data->parent_data;
|
|
data->chip->irq_mask(data);
|
|
}
|
|
|
|
/**
|
|
* irq_chip_unmask_parent - Unmask the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
*/
|
|
void irq_chip_unmask_parent(struct irq_data *data)
|
|
{
|
|
data = data->parent_data;
|
|
data->chip->irq_unmask(data);
|
|
}
|
|
|
|
/**
|
|
* irq_chip_eoi_parent - Invoke EOI on the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
*/
|
|
void irq_chip_eoi_parent(struct irq_data *data)
|
|
{
|
|
data = data->parent_data;
|
|
data->chip->irq_eoi(data);
|
|
}
|
|
|
|
/**
|
|
* irq_chip_set_affinity_parent - Set affinity on the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
* @dest: The affinity mask to set
|
|
* @force: Flag to enforce setting (disable online checks)
|
|
*
|
|
* Conditinal, as the underlying parent chip might not implement it.
|
|
*/
|
|
int irq_chip_set_affinity_parent(struct irq_data *data,
|
|
const struct cpumask *dest, bool force)
|
|
{
|
|
data = data->parent_data;
|
|
if (data->chip->irq_set_affinity)
|
|
return data->chip->irq_set_affinity(data, dest, force);
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/**
|
|
* irq_chip_set_type_parent - Set IRQ type on the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
* @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
|
|
*
|
|
* Conditional, as the underlying parent chip might not implement it.
|
|
*/
|
|
int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
|
|
{
|
|
data = data->parent_data;
|
|
|
|
if (data->chip->irq_set_type)
|
|
return data->chip->irq_set_type(data, type);
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/**
|
|
* irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
|
|
* @data: Pointer to interrupt specific data
|
|
*
|
|
* Iterate through the domain hierarchy of the interrupt and check
|
|
* whether a hw retrigger function exists. If yes, invoke it.
|
|
*/
|
|
int irq_chip_retrigger_hierarchy(struct irq_data *data)
|
|
{
|
|
for (data = data->parent_data; data; data = data->parent_data)
|
|
if (data->chip && data->chip->irq_retrigger)
|
|
return data->chip->irq_retrigger(data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
* @vcpu_info: The vcpu affinity information
|
|
*/
|
|
int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
|
|
{
|
|
data = data->parent_data;
|
|
if (data->chip->irq_set_vcpu_affinity)
|
|
return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/**
|
|
* irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
|
|
* @data: Pointer to interrupt specific data
|
|
* @on: Whether to set or reset the wake-up capability of this irq
|
|
*
|
|
* Conditional, as the underlying parent chip might not implement it.
|
|
*/
|
|
int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
|
|
{
|
|
data = data->parent_data;
|
|
if (data->chip->irq_set_wake)
|
|
return data->chip->irq_set_wake(data, on);
|
|
|
|
return -ENOSYS;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* irq_chip_compose_msi_msg - Componse msi message for a irq chip
|
|
* @data: Pointer to interrupt specific data
|
|
* @msg: Pointer to the MSI message
|
|
*
|
|
* For hierarchical domains we find the first chip in the hierarchy
|
|
* which implements the irq_compose_msi_msg callback. For non
|
|
* hierarchical we use the top level chip.
|
|
*/
|
|
int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
|
{
|
|
struct irq_data *pos = NULL;
|
|
|
|
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
|
for (; data; data = data->parent_data)
|
|
#endif
|
|
if (data->chip && data->chip->irq_compose_msi_msg)
|
|
pos = data;
|
|
if (!pos)
|
|
return -ENOSYS;
|
|
|
|
pos->chip->irq_compose_msi_msg(pos, msg);
|
|
|
|
return 0;
|
|
}
|