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038c5b6025
Patch from Bellido Nicolas Core support for AAEC-2000 based platforms. This is an updated version of the previous patch, and takes into account Russell's comments. AAED-2000 default configuration will follow as soon as some problems with the bootloader are sorted out... Signed-off-by: Nicolas Bellido Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
152 lines
6.4 KiB
C
152 lines
6.4 KiB
C
/*
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* linux/include/asm-arm/arch-aaec2000/aaec2000.h
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*
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* AAEC-2000 registers definition
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*
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* Copyright (c) 2005 Nicolas Bellido Y Ortega
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_AAEC2000_H
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#define __ASM_ARCH_AAEC2000_H
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#ifndef __ASM_ARCH_HARDWARE_H
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#error You must include hardware.h not this file
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#endif /* __ASM_ARCH_HARDWARE_H */
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/* Interrupt controller */
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#define IRQ_BASE __REG(0x80000500)
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#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
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#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
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#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
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#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
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/* UART 1 */
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#define UART1_BASE __REG(0x80000600)
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#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
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#define UART1_LCR __REG(0x80000604) /* Link Control Register */
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#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
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#define UART1_CR __REG(0x8000060c) /* Control Register */
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#define UART1_SR __REG(0x80000610) /* Status Register */
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#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */
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#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */
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#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */
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/* UART 2 */
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#define UART2_BASE __REG(0x80000700)
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#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */
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#define UART2_LCR __REG(0x80000704) /* Link Control Register */
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#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */
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#define UART2_CR __REG(0x8000070c) /* Control Register */
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#define UART2_SR __REG(0x80000710) /* Status Register */
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#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */
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#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */
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#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */
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/* UART 3 */
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#define UART3_BASE __REG(0x80000800)
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#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */
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#define UART3_LCR __REG(0x80000804) /* Link Control Register */
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#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */
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#define UART3_CR __REG(0x8000080c) /* Control Register */
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#define UART3_SR __REG(0x80000810) /* Status Register */
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#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */
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#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */
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#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */
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/* These are used in some places */
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#define _UART1_BASE __PREG(UART1_BASE)
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#define _UART2_BASE __PREG(UART2_BASE)
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#define _UART3_BASE __PREG(UART3_BASE)
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/* UART Registers Offsets */
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#define UART_DR 0x00
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#define UART_LCR 0x04
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#define UART_BRCR 0x08
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#define UART_CR 0x0c
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#define UART_SR 0x10
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#define UART_INT 0x14
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#define UART_INTM 0x18
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#define UART_INTRES 0x1c
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/* UART_LCR Bitmask */
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#define UART_LCR_BRK (1 << 0) /* Send Break */
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#define UART_LCR_PEN (1 << 1) /* Parity Enable */
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#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */
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#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */
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#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */
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#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */
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#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */
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#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */
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#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */
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/* UART_CR Bitmask */
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#define UART_CR_EN (1 << 0) /* UART Enable */
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#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */
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#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */
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#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */
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#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */
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#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */
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#define UART_CR_LOOP (1 << 6) /* Loopback Mode */
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/* UART_SR Bitmask */
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#define UART_SR_CTS (1 << 0) /* Clear To Send Status */
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#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */
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#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */
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#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */
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#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */
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#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */
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#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */
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#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */
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/* UART_INT Bitmask */
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#define UART_INT_RIS (1 << 0) /* Rx Interrupt */
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#define UART_INT_TIS (1 << 1) /* Tx Interrupt */
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#define UART_INT_MIS (1 << 2) /* Modem Interrupt */
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#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */
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/* Timer 1 */
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#define TIMER1_BASE __REG(0x80000c00)
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#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */
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#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */
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#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */
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#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */
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/* Timer 2 */
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#define TIMER2_BASE __REG(0x80000d00)
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#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */
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#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */
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#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */
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#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */
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/* Timer 3 */
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#define TIMER3_BASE __REG(0x80000e00)
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#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */
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#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */
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#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */
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#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */
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/* Timer Control register bits */
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#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start° Timer */
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#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */
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#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
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#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
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#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2)*/
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/* Power and State Control */
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#define POWER_BASE __REG(0x80000400)
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#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */
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#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */
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#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */
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#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */
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#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */
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#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */
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#define POWER_TEOI __REG(0x80000418) /* Tick EoI */
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#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
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#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
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#endif /* __ARM_ARCH_AAEC2000_H */
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