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18f2190d79
Add PPU event-based and cycle-based profiling support to Oprofile for Cell. Oprofile is expected to collect data on all CPUs simultaneously. However, there is one set of performance counters per node. There are two hardware threads or virtual CPUs on each node. Hence, OProfile must multiplex in time the performance counter collection on the two virtual CPUs. The multiplexing of the performance counters is done by a virtual counter routine. Initially, the counters are configured to collect data on the even CPUs in the system, one CPU per node. In order to capture the PC for the virtual CPU when the performance counter interrupt occurs (the specified number of events between samples has occurred), the even processors are configured to handle the performance counter interrupts for their node. The virtual counter routine is called via a kernel timer after the virtual sample time. The routine stops the counters, saves the current counts, loads the last counts for the other virtual CPU on the node, sets interrupts to be handled by the other virtual CPU and restarts the counters, the virtual timer routine is scheduled to run again. The virtual sample time is kept relatively small to make sure sampling occurs on both CPUs on the node with a relatively small granularity. Whenever the counters overflow, the performance counter interrupt is called to collect the PC for the CPU where data is being collected. The oprofile driver relies on a firmware RTAS call to setup the debug bus to route the desired signals to the performance counter hardware to be counted. The RTAS call must set the routing registers appropriately in each of the islands to pass the signals down the debug bus as well as routing the signals from a particular island onto the bus. There is a second firmware RTAS call to reset the debug bus to the non pass thru state when the counters are not in use. Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
216 lines
4.0 KiB
C
216 lines
4.0 KiB
C
/*
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Based on alpha version.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
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#define _ASM_POWERPC_OPROFILE_IMPL_H
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#ifdef __KERNEL__
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#define OP_MAX_COUNTER 8
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/* Per-counter configuration as set via oprofilefs. */
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struct op_counter_config {
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unsigned long enabled;
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unsigned long event;
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unsigned long count;
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/* Classic doesn't support per-counter user/kernel selection */
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unsigned long kernel;
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unsigned long user;
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unsigned long unit_mask;
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};
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/* System-wide configuration as set via oprofilefs. */
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struct op_system_config {
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#ifdef CONFIG_PPC64
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unsigned long mmcr0;
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unsigned long mmcr1;
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unsigned long mmcra;
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#endif
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unsigned long enable_kernel;
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unsigned long enable_user;
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};
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/* Per-arch configuration */
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struct op_powerpc_model {
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void (*reg_setup) (struct op_counter_config *,
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struct op_system_config *,
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int num_counters);
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void (*cpu_setup) (struct op_counter_config *);
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void (*start) (struct op_counter_config *);
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void (*global_start) (struct op_counter_config *);
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void (*stop) (void);
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void (*global_stop) (void);
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void (*handle_interrupt) (struct pt_regs *,
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struct op_counter_config *);
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int num_counters;
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};
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extern struct op_powerpc_model op_model_fsl_booke;
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extern struct op_powerpc_model op_model_rs64;
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extern struct op_powerpc_model op_model_power4;
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extern struct op_powerpc_model op_model_7450;
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extern struct op_powerpc_model op_model_cell;
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#ifndef CONFIG_FSL_BOOKE
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/* All the classic PPC parts use these */
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static inline unsigned int ctr_read(unsigned int i)
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{
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switch(i) {
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case 0:
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return mfspr(SPRN_PMC1);
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case 1:
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return mfspr(SPRN_PMC2);
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case 2:
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return mfspr(SPRN_PMC3);
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case 3:
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return mfspr(SPRN_PMC4);
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case 4:
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return mfspr(SPRN_PMC5);
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case 5:
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return mfspr(SPRN_PMC6);
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/* No PPC32 chip has more than 6 so far */
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#ifdef CONFIG_PPC64
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case 6:
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return mfspr(SPRN_PMC7);
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case 7:
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return mfspr(SPRN_PMC8);
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#endif
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default:
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return 0;
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}
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}
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static inline void ctr_write(unsigned int i, unsigned int val)
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{
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switch(i) {
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case 0:
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mtspr(SPRN_PMC1, val);
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break;
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case 1:
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mtspr(SPRN_PMC2, val);
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break;
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case 2:
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mtspr(SPRN_PMC3, val);
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break;
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case 3:
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mtspr(SPRN_PMC4, val);
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break;
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case 4:
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mtspr(SPRN_PMC5, val);
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break;
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case 5:
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mtspr(SPRN_PMC6, val);
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break;
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/* No PPC32 chip has more than 6, yet */
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#ifdef CONFIG_PPC64
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case 6:
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mtspr(SPRN_PMC7, val);
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break;
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case 7:
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mtspr(SPRN_PMC8, val);
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break;
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#endif
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default:
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break;
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}
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}
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#else /* CONFIG_FSL_BOOKE */
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static inline u32 get_pmlca(int ctr)
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{
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u32 pmlca;
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switch (ctr) {
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case 0:
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pmlca = mfpmr(PMRN_PMLCA0);
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break;
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case 1:
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pmlca = mfpmr(PMRN_PMLCA1);
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break;
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case 2:
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pmlca = mfpmr(PMRN_PMLCA2);
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break;
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case 3:
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pmlca = mfpmr(PMRN_PMLCA3);
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break;
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default:
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panic("Bad ctr number\n");
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}
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return pmlca;
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}
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static inline void set_pmlca(int ctr, u32 pmlca)
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{
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switch (ctr) {
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case 0:
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mtpmr(PMRN_PMLCA0, pmlca);
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break;
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case 1:
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mtpmr(PMRN_PMLCA1, pmlca);
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break;
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case 2:
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mtpmr(PMRN_PMLCA2, pmlca);
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break;
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case 3:
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mtpmr(PMRN_PMLCA3, pmlca);
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break;
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default:
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panic("Bad ctr number\n");
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}
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}
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static inline unsigned int ctr_read(unsigned int i)
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{
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switch(i) {
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case 0:
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return mfpmr(PMRN_PMC0);
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case 1:
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return mfpmr(PMRN_PMC1);
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case 2:
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return mfpmr(PMRN_PMC2);
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case 3:
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return mfpmr(PMRN_PMC3);
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default:
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return 0;
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}
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}
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static inline void ctr_write(unsigned int i, unsigned int val)
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{
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switch(i) {
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case 0:
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mtpmr(PMRN_PMC0, val);
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break;
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case 1:
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mtpmr(PMRN_PMC1, val);
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break;
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case 2:
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mtpmr(PMRN_PMC2, val);
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break;
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case 3:
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mtpmr(PMRN_PMC3, val);
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break;
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default:
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break;
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}
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}
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#endif /* CONFIG_FSL_BOOKE */
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extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
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