Martin Blumenstingl 7cafc01744 phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-on ... The vendor driver unsets the set_iddig bit during power-on as well and sets it when suspending the PHY. I did not notice this in the vendor driver first, because it's part of the dwc_otg driver there (instead of their PHY code). While here, also add all other REG_DBG_UART register bit definitions. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-6-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2020-05-15 13:16:55 +05:30
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Kconfig	phy: amlogic: meson8b-usb2: Use a MMIO regmap	2020-05-15 13:16:55 +05:30
Makefile	phy: amlogic: Add Amlogic AXG PCIE PHY Driver	2020-03-04 10:53:30 +00:00
phy-meson8b-usb2.c	phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-on	2020-05-15 13:16:55 +05:30
phy-meson-axg-mipi-pcie-analog.c	phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver	2020-03-04 10:53:30 +00:00
phy-meson-axg-pcie.c	phy: amlogic: Add Amlogic AXG PCIE PHY Driver	2020-03-04 10:53:30 +00:00
phy-meson-g12a-usb2.c	phy: amlogic: Add Amlogic A1 USB2 PHY Driver	2020-03-20 19:34:29 +05:30
phy-meson-g12a-usb3-pcie.c	phy: meson-g12a-usb3-pcie: Add support for PCIe mode	2019-10-15 14:57:32 +01:00
phy-meson-gxl-usb2.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446	2019-06-05 17:37:18 +02:00
phy-meson-gxl-usb3.c	phy: core: rework phy_set_mode to accept phy mode and submode	2018-12-12 10:01:33 +05:30