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29c4dfd92e
The non-rt signal handling was never really used, so we don't break anything. This patch also cleans up the signal stack-frame to make it independent from the processor configuration. It also improves the method used for controlling single-stepping. We now save and restore the 'icountlevel' register that controls single stepping and set or clear the saved state to enable or disable it. Signed-off-by: Chris Zankel <chris@zankel.net>
86 lines
2.5 KiB
C
86 lines
2.5 KiB
C
/*
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* include/asm-xtensa/coprocessor.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_COPROCESSOR_H
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#define _XTENSA_COPROCESSOR_H
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#include <asm/variant/core.h>
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#include <asm/variant/tie.h>
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#if !XCHAL_HAVE_CP
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#define XTENSA_CP_EXTRA_OFFSET 0
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#define XTENSA_CP_EXTRA_ALIGN 1 /* must be a power of 2 */
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#define XTENSA_CP_EXTRA_SIZE 0
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#else
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#define XTOFS(last_start,last_size,align) \
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((last_start+last_size+align-1) & -align)
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#define XTENSA_CP_EXTRA_OFFSET 0
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#define XTENSA_CP_EXTRA_ALIGN XCHAL_EXTRA_SA_ALIGN
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#define XTENSA_CPE_CP0_OFFSET \
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XTOFS(XTENSA_CP_EXTRA_OFFSET, XCHAL_EXTRA_SA_SIZE, XCHAL_CP0_SA_ALIGN)
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#define XTENSA_CPE_CP1_OFFSET \
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XTOFS(XTENSA_CPE_CP0_OFFSET, XCHAL_CP0_SA_SIZE, XCHAL_CP1_SA_ALIGN)
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#define XTENSA_CPE_CP2_OFFSET \
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XTOFS(XTENSA_CPE_CP1_OFFSET, XCHAL_CP1_SA_SIZE, XCHAL_CP2_SA_ALIGN)
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#define XTENSA_CPE_CP3_OFFSET \
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XTOFS(XTENSA_CPE_CP2_OFFSET, XCHAL_CP2_SA_SIZE, XCHAL_CP3_SA_ALIGN)
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#define XTENSA_CPE_CP4_OFFSET \
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XTOFS(XTENSA_CPE_CP3_OFFSET, XCHAL_CP3_SA_SIZE, XCHAL_CP4_SA_ALIGN)
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#define XTENSA_CPE_CP5_OFFSET \
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XTOFS(XTENSA_CPE_CP4_OFFSET, XCHAL_CP4_SA_SIZE, XCHAL_CP5_SA_ALIGN)
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#define XTENSA_CPE_CP6_OFFSET \
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XTOFS(XTENSA_CPE_CP5_OFFSET, XCHAL_CP5_SA_SIZE, XCHAL_CP6_SA_ALIGN)
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#define XTENSA_CPE_CP7_OFFSET \
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XTOFS(XTENSA_CPE_CP6_OFFSET, XCHAL_CP6_SA_SIZE, XCHAL_CP7_SA_ALIGN)
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#define XTENSA_CP_EXTRA_SIZE \
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XTOFS(XTENSA_CPE_CP7_OFFSET, XCHAL_CP7_SA_SIZE, 16)
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#if XCHAL_CP_NUM > 0
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# ifndef __ASSEMBLY__
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/*
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* Tasks that own contents of (last user) each coprocessor.
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* Entries are 0 for not-owned or non-existent coprocessors.
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* Note: The size of this structure is fixed to 8 bytes in entry.S
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*/
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typedef struct {
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struct task_struct *owner; /* owner */
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int offset; /* offset in cpextra space. */
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} coprocessor_info_t;
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# else
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# define COPROCESSOR_INFO_OWNER 0
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# define COPROCESSOR_INFO_OFFSET 4
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# define COPROCESSOR_INFO_SIZE 8
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# endif
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#endif
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#endif /* XCHAL_HAVE_CP */
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#ifndef __ASSEMBLY__
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# if XCHAL_CP_NUM > 0
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struct task_struct;
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extern void release_coprocessors (struct task_struct*);
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extern void save_coprocessor_registers(void*, int);
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# else
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# define release_coprocessors(task)
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# endif
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typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE]
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__attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
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#endif /* !__ASSEMBLY__ */
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#endif /* _XTENSA_COPROCESSOR_H */
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