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This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
118 lines
3.0 KiB
C
118 lines
3.0 KiB
C
/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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#include "berlin2-div.h"
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struct berlin2_pll_map {
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const u8 vcodiv[16];
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u8 mult;
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u8 fbdiv_shift;
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u8 rfdiv_shift;
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u8 divsel_shift;
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};
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struct berlin2_pll {
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struct clk_hw hw;
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void __iomem *base;
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struct berlin2_pll_map map;
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};
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#define to_berlin2_pll(hw) container_of(hw, struct berlin2_pll, hw)
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#define SPLL_CTRL0 0x00
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#define SPLL_CTRL1 0x04
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#define SPLL_CTRL2 0x08
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#define SPLL_CTRL3 0x0c
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#define SPLL_CTRL4 0x10
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#define FBDIV_MASK 0x1ff
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#define RFDIV_MASK 0x1f
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#define DIVSEL_MASK 0xf
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/*
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* The output frequency formula for the pll is:
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* clkout = fbdiv / refdiv * parent / vcodiv
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*/
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static unsigned long
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berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct berlin2_pll *pll = to_berlin2_pll(hw);
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struct berlin2_pll_map *map = &pll->map;
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u32 val, fbdiv, rfdiv, vcodivsel, vcodiv;
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u64 rate = parent_rate;
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val = readl_relaxed(pll->base + SPLL_CTRL0);
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fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
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rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;
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if (rfdiv == 0) {
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pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
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rfdiv = 1;
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}
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val = readl_relaxed(pll->base + SPLL_CTRL1);
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vcodivsel = (val >> map->divsel_shift) & DIVSEL_MASK;
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vcodiv = map->vcodiv[vcodivsel];
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if (vcodiv == 0) {
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pr_warn("%s has zero vcodiv (index %d)\n",
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__clk_get_name(hw->clk), vcodivsel);
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vcodiv = 1;
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}
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rate *= fbdiv * map->mult;
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do_div(rate, rfdiv * vcodiv);
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return (unsigned long)rate;
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}
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static const struct clk_ops berlin2_pll_ops = {
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.recalc_rate = berlin2_pll_recalc_rate,
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};
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struct clk * __init
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berlin2_pll_register(const struct berlin2_pll_map *map,
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void __iomem *base, const char *name,
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const char *parent_name, unsigned long flags)
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{
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struct clk_init_data init;
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struct berlin2_pll *pll;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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/* copy pll_map to allow __initconst */
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memcpy(&pll->map, map, sizeof(*map));
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pll->base = base;
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pll->hw.init = &init;
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init.name = name;
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init.ops = &berlin2_pll_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = flags;
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return clk_register(NULL, &pll->hw);
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}
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