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1fa8d07ae1
On Tegra186, secure world applications may need to access host1x
during suspend/resume, and rely on the kernel to keep Host1x out
of reset during the suspend cycle. As such, as a quirk,
skip asserting Host1x's reset on Tegra186.
We don't need to keep the clocks enabled, as BPMP ensures the clock
stays on while Host1x is being used. On newer SoC's, the reset line
is inaccessible, so there is no need for the quirk.
Fixes: b7c00cdf6d ("gpu: host1x: Enable system suspend callbacks")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240222010517.1573931-1-cyndis@kapsi.fi
358 lines
9.6 KiB
C
358 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2015, NVIDIA Corporation.
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*/
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#ifndef HOST1X_DEV_H
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#define HOST1X_DEV_H
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#include <linux/device.h>
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#include <linux/iommu.h>
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#include <linux/iova.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "cdma.h"
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#include "channel.h"
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#include "context.h"
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#include "intr.h"
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#include "job.h"
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#include "syncpt.h"
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struct host1x_syncpt;
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struct host1x_syncpt_base;
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struct host1x_channel;
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struct host1x_cdma;
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struct host1x_job;
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struct push_buffer;
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struct output;
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struct dentry;
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struct host1x_channel_ops {
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int (*init)(struct host1x_channel *channel, struct host1x *host,
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unsigned int id);
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int (*submit)(struct host1x_job *job);
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};
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struct host1x_cdma_ops {
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void (*start)(struct host1x_cdma *cdma);
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void (*stop)(struct host1x_cdma *cdma);
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void (*flush)(struct host1x_cdma *cdma);
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int (*timeout_init)(struct host1x_cdma *cdma);
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void (*timeout_destroy)(struct host1x_cdma *cdma);
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void (*freeze)(struct host1x_cdma *cdma);
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void (*resume)(struct host1x_cdma *cdma, u32 getptr);
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void (*timeout_cpu_incr)(struct host1x_cdma *cdma, u32 getptr,
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u32 syncpt_incrs, u32 syncval, u32 nr_slots);
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};
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struct host1x_pushbuffer_ops {
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void (*init)(struct push_buffer *pb);
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};
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struct host1x_debug_ops {
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void (*debug_init)(struct dentry *de);
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void (*show_channel_cdma)(struct host1x *host,
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struct host1x_channel *ch,
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struct output *o);
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void (*show_channel_fifo)(struct host1x *host,
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struct host1x_channel *ch,
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struct output *o);
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void (*show_mlocks)(struct host1x *host, struct output *output);
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};
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struct host1x_syncpt_ops {
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void (*restore)(struct host1x_syncpt *syncpt);
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void (*restore_wait_base)(struct host1x_syncpt *syncpt);
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void (*load_wait_base)(struct host1x_syncpt *syncpt);
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u32 (*load)(struct host1x_syncpt *syncpt);
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int (*cpu_incr)(struct host1x_syncpt *syncpt);
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void (*assign_to_channel)(struct host1x_syncpt *syncpt,
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struct host1x_channel *channel);
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void (*enable_protection)(struct host1x *host);
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};
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struct host1x_intr_ops {
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int (*init_host_sync)(struct host1x *host, u32 cpm);
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void (*set_syncpt_threshold)(
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struct host1x *host, unsigned int id, u32 thresh);
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void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
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void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
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void (*disable_all_syncpt_intrs)(struct host1x *host);
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int (*free_syncpt_irq)(struct host1x *host);
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};
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struct host1x_sid_entry {
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unsigned int base;
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unsigned int offset;
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unsigned int limit;
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};
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struct host1x_table_desc {
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unsigned int base;
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unsigned int count;
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};
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struct host1x_info {
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unsigned int nb_channels; /* host1x: number of channels supported */
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unsigned int nb_pts; /* host1x: number of syncpoints supported */
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unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
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unsigned int nb_mlocks; /* host1x: number of mlocks supported */
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int (*init)(struct host1x *host1x); /* initialize per SoC ops */
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unsigned int sync_offset; /* offset of syncpoint registers */
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u64 dma_mask; /* mask of addressable memory */
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bool has_wide_gather; /* supports GATHER_W opcode */
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bool has_hypervisor; /* has hypervisor registers */
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bool has_common; /* has common registers separate from hypervisor */
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unsigned int num_sid_entries;
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const struct host1x_sid_entry *sid_table;
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struct host1x_table_desc streamid_vm_table;
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struct host1x_table_desc classid_vm_table;
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struct host1x_table_desc mmio_vm_table;
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/*
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* On T20-T148, the boot chain may setup DC to increment syncpoints
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* 26/27 on VBLANK. As such we cannot use these syncpoints until
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* the display driver disables VBLANK increments.
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*/
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bool reserve_vblank_syncpts;
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/*
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* On Tegra186, secure world applications may require access to
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* host1x during suspend/resume. To allow this, we need to leave
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* host1x not in reset.
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*/
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bool skip_reset_assert;
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};
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struct host1x {
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const struct host1x_info *info;
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void __iomem *regs;
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void __iomem *hv_regs; /* hypervisor region */
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void __iomem *common_regs;
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int syncpt_irqs[8];
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int num_syncpt_irqs;
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struct host1x_syncpt *syncpt;
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struct host1x_syncpt_base *bases;
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struct device *dev;
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struct clk *clk;
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struct reset_control_bulk_data resets[2];
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unsigned int nresets;
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struct iommu_group *group;
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struct iommu_domain *domain;
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struct iova_domain iova;
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dma_addr_t iova_end;
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struct mutex intr_mutex;
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const struct host1x_syncpt_ops *syncpt_op;
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const struct host1x_intr_ops *intr_op;
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const struct host1x_channel_ops *channel_op;
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const struct host1x_cdma_ops *cdma_op;
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const struct host1x_pushbuffer_ops *cdma_pb_op;
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const struct host1x_debug_ops *debug_op;
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struct host1x_syncpt *nop_sp;
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struct mutex syncpt_mutex;
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struct host1x_channel_list channel_list;
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struct host1x_memory_context_list context_list;
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struct dentry *debugfs;
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struct mutex devices_lock;
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struct list_head devices;
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struct list_head list;
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struct device_dma_parameters dma_parms;
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struct host1x_bo_cache cache;
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};
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void host1x_common_writel(struct host1x *host1x, u32 v, u32 r);
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void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);
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u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);
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void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);
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u32 host1x_sync_readl(struct host1x *host1x, u32 r);
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void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v);
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u32 host1x_ch_readl(struct host1x_channel *ch, u32 r);
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static inline void host1x_hw_syncpt_restore(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->restore(sp);
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}
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static inline void host1x_hw_syncpt_restore_wait_base(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->restore_wait_base(sp);
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}
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static inline void host1x_hw_syncpt_load_wait_base(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->load_wait_base(sp);
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}
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static inline u32 host1x_hw_syncpt_load(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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return host->syncpt_op->load(sp);
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}
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static inline int host1x_hw_syncpt_cpu_incr(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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return host->syncpt_op->cpu_incr(sp);
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}
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static inline void host1x_hw_syncpt_assign_to_channel(
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struct host1x *host, struct host1x_syncpt *sp,
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struct host1x_channel *ch)
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{
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return host->syncpt_op->assign_to_channel(sp, ch);
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}
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static inline void host1x_hw_syncpt_enable_protection(struct host1x *host)
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{
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return host->syncpt_op->enable_protection(host);
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}
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static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm)
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{
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return host->intr_op->init_host_sync(host, cpm);
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}
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static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host,
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unsigned int id,
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u32 thresh)
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{
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host->intr_op->set_syncpt_threshold(host, id, thresh);
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}
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static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host,
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unsigned int id)
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{
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host->intr_op->enable_syncpt_intr(host, id);
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}
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static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host,
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unsigned int id)
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{
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host->intr_op->disable_syncpt_intr(host, id);
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}
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static inline void host1x_hw_intr_disable_all_syncpt_intrs(struct host1x *host)
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{
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host->intr_op->disable_all_syncpt_intrs(host);
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}
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static inline int host1x_hw_intr_free_syncpt_irq(struct host1x *host)
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{
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return host->intr_op->free_syncpt_irq(host);
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}
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static inline int host1x_hw_channel_init(struct host1x *host,
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struct host1x_channel *channel,
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unsigned int id)
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{
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return host->channel_op->init(channel, host, id);
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}
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static inline int host1x_hw_channel_submit(struct host1x *host,
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struct host1x_job *job)
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{
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return host->channel_op->submit(job);
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}
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static inline void host1x_hw_cdma_start(struct host1x *host,
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struct host1x_cdma *cdma)
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{
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host->cdma_op->start(cdma);
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}
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static inline void host1x_hw_cdma_stop(struct host1x *host,
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struct host1x_cdma *cdma)
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{
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host->cdma_op->stop(cdma);
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}
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static inline void host1x_hw_cdma_flush(struct host1x *host,
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struct host1x_cdma *cdma)
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{
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host->cdma_op->flush(cdma);
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}
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static inline int host1x_hw_cdma_timeout_init(struct host1x *host,
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struct host1x_cdma *cdma)
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{
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return host->cdma_op->timeout_init(cdma);
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}
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static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host,
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struct host1x_cdma *cdma)
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{
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host->cdma_op->timeout_destroy(cdma);
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}
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static inline void host1x_hw_cdma_freeze(struct host1x *host,
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struct host1x_cdma *cdma)
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{
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host->cdma_op->freeze(cdma);
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}
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static inline void host1x_hw_cdma_resume(struct host1x *host,
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struct host1x_cdma *cdma, u32 getptr)
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{
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host->cdma_op->resume(cdma, getptr);
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}
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static inline void host1x_hw_cdma_timeout_cpu_incr(struct host1x *host,
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struct host1x_cdma *cdma,
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u32 getptr,
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u32 syncpt_incrs,
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u32 syncval, u32 nr_slots)
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{
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host->cdma_op->timeout_cpu_incr(cdma, getptr, syncpt_incrs, syncval,
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nr_slots);
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}
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static inline void host1x_hw_pushbuffer_init(struct host1x *host,
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struct push_buffer *pb)
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{
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host->cdma_pb_op->init(pb);
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}
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static inline void host1x_hw_debug_init(struct host1x *host, struct dentry *de)
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{
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if (host->debug_op && host->debug_op->debug_init)
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host->debug_op->debug_init(de);
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}
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static inline void host1x_hw_show_channel_cdma(struct host1x *host,
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struct host1x_channel *channel,
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struct output *o)
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{
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host->debug_op->show_channel_cdma(host, channel, o);
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}
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static inline void host1x_hw_show_channel_fifo(struct host1x *host,
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struct host1x_channel *channel,
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struct output *o)
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{
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host->debug_op->show_channel_fifo(host, channel, o);
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}
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static inline void host1x_hw_show_mlocks(struct host1x *host, struct output *o)
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{
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host->debug_op->show_mlocks(host, o);
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}
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extern struct platform_driver tegra_mipi_driver;
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#endif
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