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Add MT8188 VDOSYS0 and VDOSYS1 reset control bits. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
117 lines
4.5 KiB
C
117 lines
4.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Runyang Chen <runyang.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8188
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#define MT8188_TOPRGU_CONN_MCU_SW_RST 0
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#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1
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#define MT8188_TOPRGU_IPU0_SW_RST 2
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#define MT8188_TOPRGU_IPU1_SW_RST 3
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#define MT8188_TOPRGU_IPU2_SW_RST 4
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#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5
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#define MT8188_TOPRGU_INFRA_SW_RST 6
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#define MT8188_TOPRGU_MMSYS_SW_RST 7
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#define MT8188_TOPRGU_MFG_SW_RST 8
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#define MT8188_TOPRGU_VENC_SW_RST 9
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#define MT8188_TOPRGU_VDEC_SW_RST 10
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#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11
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#define MT8188_TOPRGU_SCP_SW_RST 12
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#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13
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#define MT8188_TOPRGU_AUDIO_SW_RST 14
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#define MT8188_TOPRGU_CAMSYS_SW_RST 15
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#define MT8188_TOPRGU_MJC_SW_RST 16
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#define MT8188_TOPRGU_PERI_SW_RST 17
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#define MT8188_TOPRGU_PERI_AO_SW_RST 18
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#define MT8188_TOPRGU_PCIE_SW_RST 19
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#define MT8188_TOPRGU_ADSPSYS_SW_RST 21
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#define MT8188_TOPRGU_DPTX_SW_RST 22
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#define MT8188_TOPRGU_SPMI_MST_SW_RST 23
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#define MT8188_TOPRGU_SW_RST_NUM 24
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/* INFRA resets */
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#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0
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#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1
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#define MT8188_INFRA_RST3_PTP_CTRL_RST 2
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#define MT8188_VDO0_RST_DISP_OVL0 0
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#define MT8188_VDO0_RST_FAKE_ENG0 1
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#define MT8188_VDO0_RST_DISP_CCORR0 2
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#define MT8188_VDO0_RST_DISP_MUTEX0 3
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#define MT8188_VDO0_RST_DISP_GAMMA0 4
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#define MT8188_VDO0_RST_DISP_DITHER0 5
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#define MT8188_VDO0_RST_DISP_WDMA0 6
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#define MT8188_VDO0_RST_DISP_RDMA0 7
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#define MT8188_VDO0_RST_DSI0 8
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#define MT8188_VDO0_RST_DSI1 9
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#define MT8188_VDO0_RST_DSC_WRAP0 10
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#define MT8188_VDO0_RST_VPP_MERGE0 11
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#define MT8188_VDO0_RST_DP_INTF0 12
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#define MT8188_VDO0_RST_DISP_AAL0 13
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#define MT8188_VDO0_RST_INLINEROT0 14
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#define MT8188_VDO0_RST_APB_BUS 15
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#define MT8188_VDO0_RST_DISP_COLOR0 16
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#define MT8188_VDO0_RST_MDP_WROT0 17
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#define MT8188_VDO0_RST_DISP_RSZ0 18
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#define MT8188_VDO1_RST_SMI_LARB2 0
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#define MT8188_VDO1_RST_SMI_LARB3 1
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#define MT8188_VDO1_RST_GALS 2
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#define MT8188_VDO1_RST_FAKE_ENG0 3
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#define MT8188_VDO1_RST_FAKE_ENG1 4
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#define MT8188_VDO1_RST_MDP_RDMA0 5
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#define MT8188_VDO1_RST_MDP_RDMA1 6
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#define MT8188_VDO1_RST_MDP_RDMA2 7
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#define MT8188_VDO1_RST_MDP_RDMA3 8
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#define MT8188_VDO1_RST_VPP_MERGE0 9
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#define MT8188_VDO1_RST_VPP_MERGE1 10
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#define MT8188_VDO1_RST_VPP_MERGE2 11
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#define MT8188_VDO1_RST_VPP_MERGE3 12
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#define MT8188_VDO1_RST_VPP_MERGE4 13
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#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14
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#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15
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#define MT8188_VDO1_RST_DISP_MUTEX 16
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#define MT8188_VDO1_RST_MDP_RDMA4 17
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#define MT8188_VDO1_RST_MDP_RDMA5 18
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#define MT8188_VDO1_RST_MDP_RDMA6 19
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#define MT8188_VDO1_RST_MDP_RDMA7 20
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#define MT8188_VDO1_RST_DP_INTF1_MMCK 21
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#define MT8188_VDO1_RST_DPI0_MM_CK 22
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#define MT8188_VDO1_RST_DPI1_MM_CK 23
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#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24
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#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25
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#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26
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#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27
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#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28
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#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29
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#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30
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#define MT8188_VDO1_RST_PADDING0 31
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#define MT8188_VDO1_RST_PADDING1 32
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#define MT8188_VDO1_RST_PADDING2 33
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#define MT8188_VDO1_RST_PADDING3 34
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#define MT8188_VDO1_RST_PADDING4 35
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#define MT8188_VDO1_RST_PADDING5 36
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#define MT8188_VDO1_RST_PADDING6 37
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#define MT8188_VDO1_RST_PADDING7 38
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#define MT8188_VDO1_RST_DISP_RSZ0 39
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#define MT8188_VDO1_RST_DISP_RSZ1 40
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#define MT8188_VDO1_RST_DISP_RSZ2 41
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#define MT8188_VDO1_RST_DISP_RSZ3 42
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#define MT8188_VDO1_RST_HDR_VDO_FE0 43
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#define MT8188_VDO1_RST_HDR_GFX_FE0 44
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#define MT8188_VDO1_RST_HDR_VDO_BE 45
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#define MT8188_VDO1_RST_HDR_VDO_FE1 46
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#define MT8188_VDO1_RST_HDR_GFX_FE1 47
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#define MT8188_VDO1_RST_DISP_MIXER 48
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#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49
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#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50
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#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51
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#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
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#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
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