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01be5d63fd
Leaving this configurable caused more trouble than it was ever worth, so just make it explicit. Boards that are verified one way or the other can fix up their selects accordingly. We presently default to non-coherent for most platforms. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
#ifndef __ASM_SH_PCI_H
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#define __ASM_SH_PCI_H
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#ifdef __KERNEL__
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/* Can be used to override the logic in pci_scan_bus for skipping
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already-configured bus numbers - to be used for buggy BIOSes
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or architectures with incomplete PCI setup by the loader */
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#define pcibios_assign_all_busses() 1
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/*
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* A board can define one or more PCI channels that represent built-in (or
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* external) PCI controllers.
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*/
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struct pci_channel {
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struct pci_channel *next;
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struct pci_ops *pci_ops;
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struct resource *io_resource;
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struct resource *mem_resource;
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unsigned long io_offset;
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unsigned long mem_offset;
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unsigned long reg_base;
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unsigned long io_map_base;
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};
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extern void register_pci_controller(struct pci_channel *hose);
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extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
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struct pci_dev;
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#define HAVE_PCI_MMAP
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extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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extern void pcibios_set_master(struct pci_dev *dev);
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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/* Dynamic DMA mapping stuff.
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* SuperH has everything mapped statically like x86.
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*/
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/* The PCI address space does equal the physical memory
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* address space. The networking and block device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
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/* pci_unmap_{single,page} being a nop depends upon the
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* configuration.
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*/
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#ifdef CONFIG_DMA_NONCOHERENT
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
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#else
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
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#define pci_unmap_addr(PTR, ADDR_NAME) (0)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
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#define pci_unmap_len(PTR, LEN_NAME) (0)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
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#endif
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#ifdef CONFIG_PCI
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/*
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* None of the SH PCI controllers support MWI, it is always treated as a
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* direct memory write.
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*/
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#define PCI_DISABLE_MWI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = L1_CACHE_BYTES;
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else
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cacheline_size = byte << 2;
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*strat = PCI_DMA_BURST_MULTIPLE;
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*strategy_parameter = cacheline_size;
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}
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#endif
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#ifdef CONFIG_SUPERH32
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/*
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* If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
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* at the end of the address space in a special non-translatable area.
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*/
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#define PCI_MEM_FIXED_START 0xfd000000
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#define PCI_MEM_FIXED_END (PCI_MEM_FIXED_START + 0x01000000)
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#define is_pci_memory_fixed_range(s, e) \
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((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
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#else
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#define is_pci_memory_fixed_range(s, e) (0)
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#endif
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/* Board-specific fixup routines. */
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int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
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extern void pcibios_resource_to_bus(struct pci_dev *dev,
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struct pci_bus_region *region, struct resource *res);
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extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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/* Chances are this interrupt is wired PC-style ... */
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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return channel ? 15 : 14;
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}
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/* generic DMA-mapping stuff */
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#include <asm-generic/pci-dma-compat.h>
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_PCI_H */
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