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On some devices (e.g. Samsung Galaxy A5 (2015)), the bootloader seems to keep interrupts enabled for SM5502 when booting Linux. Changing the cable state (i.e. plugging in a cable) - until the driver is loaded - will therefore produce an interrupt that is never read. In this situation, the cable state will be stuck forever on the initial state because SM5502 stops sending interrupts. This can be avoided by clearing those pending interrupts after the driver has been loaded. One way to do this is to reset all registers to default state by writing to SM5502_REG_RESET. This ensures that we start from a clean state, with all interrupts disabled. Suggested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
281 lines
11 KiB
C
281 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* sm5502.h
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd
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*/
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#ifndef __LINUX_EXTCON_SM5502_H
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#define __LINUX_EXTCON_SM5502_H
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enum sm5502_types {
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TYPE_SM5502,
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};
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/* SM5502 registers */
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enum sm5502_reg {
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SM5502_REG_DEVICE_ID = 0x01,
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SM5502_REG_CONTROL,
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SM5502_REG_INT1,
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SM5502_REG_INT2,
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SM5502_REG_INTMASK1,
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SM5502_REG_INTMASK2,
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SM5502_REG_ADC,
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SM5502_REG_TIMING_SET1,
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SM5502_REG_TIMING_SET2,
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SM5502_REG_DEV_TYPE1,
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SM5502_REG_DEV_TYPE2,
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SM5502_REG_BUTTON1,
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SM5502_REG_BUTTON2,
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SM5502_REG_CAR_KIT_STATUS,
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SM5502_REG_RSVD1,
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SM5502_REG_RSVD2,
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SM5502_REG_RSVD3,
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SM5502_REG_RSVD4,
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SM5502_REG_MANUAL_SW1,
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SM5502_REG_MANUAL_SW2,
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SM5502_REG_DEV_TYPE3,
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SM5502_REG_RSVD5,
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SM5502_REG_RSVD6,
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SM5502_REG_RSVD7,
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SM5502_REG_RSVD8,
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SM5502_REG_RSVD9,
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SM5502_REG_RESET,
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SM5502_REG_RSVD10,
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SM5502_REG_RESERVED_ID1,
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SM5502_REG_RSVD11,
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SM5502_REG_RSVD12,
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SM5502_REG_RESERVED_ID2,
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SM5502_REG_RSVD13,
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SM5502_REG_OCP,
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SM5502_REG_RSVD14,
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SM5502_REG_RSVD15,
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SM5502_REG_RSVD16,
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SM5502_REG_RSVD17,
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SM5502_REG_RSVD18,
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SM5502_REG_RSVD19,
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SM5502_REG_RSVD20,
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SM5502_REG_RSVD21,
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SM5502_REG_RSVD22,
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SM5502_REG_RSVD23,
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SM5502_REG_RSVD24,
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SM5502_REG_RSVD25,
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SM5502_REG_RSVD26,
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SM5502_REG_RSVD27,
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SM5502_REG_RSVD28,
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SM5502_REG_RSVD29,
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SM5502_REG_RSVD30,
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SM5502_REG_RSVD31,
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SM5502_REG_RSVD32,
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SM5502_REG_RSVD33,
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SM5502_REG_RSVD34,
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SM5502_REG_RSVD35,
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SM5502_REG_RSVD36,
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SM5502_REG_RESERVED_ID3,
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SM5502_REG_END,
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};
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/* Define SM5502 MASK/SHIFT constant */
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#define SM5502_REG_DEVICE_ID_VENDOR_SHIFT 0
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#define SM5502_REG_DEVICE_ID_VERSION_SHIFT 3
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#define SM5502_REG_DEVICE_ID_VENDOR_MASK (0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT)
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#define SM5502_REG_DEVICE_ID_VERSION_MASK (0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT)
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#define SM5502_REG_CONTROL_MASK_INT_SHIFT 0
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#define SM5502_REG_CONTROL_WAIT_SHIFT 1
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#define SM5502_REG_CONTROL_MANUAL_SW_SHIFT 2
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#define SM5502_REG_CONTROL_RAW_DATA_SHIFT 3
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#define SM5502_REG_CONTROL_SW_OPEN_SHIFT 4
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#define SM5502_REG_CONTROL_MASK_INT_MASK (0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT)
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#define SM5502_REG_CONTROL_WAIT_MASK (0x1 << SM5502_REG_CONTROL_WAIT_SHIFT)
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#define SM5502_REG_CONTROL_MANUAL_SW_MASK (0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT)
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#define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
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#define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
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#define SM5502_REG_INTM1_ATTACH_SHIFT 0
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#define SM5502_REG_INTM1_DETACH_SHIFT 1
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#define SM5502_REG_INTM1_KP_SHIFT 2
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#define SM5502_REG_INTM1_LKP_SHIFT 3
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#define SM5502_REG_INTM1_LKR_SHIFT 4
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#define SM5502_REG_INTM1_OVP_EVENT_SHIFT 5
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#define SM5502_REG_INTM1_OCP_EVENT_SHIFT 6
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#define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT 7
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#define SM5502_REG_INTM1_ATTACH_MASK (0x1 << SM5502_REG_INTM1_ATTACH_SHIFT)
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#define SM5502_REG_INTM1_DETACH_MASK (0x1 << SM5502_REG_INTM1_DETACH_SHIFT)
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#define SM5502_REG_INTM1_KP_MASK (0x1 << SM5502_REG_INTM1_KP_SHIFT)
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#define SM5502_REG_INTM1_LKP_MASK (0x1 << SM5502_REG_INTM1_LKP_SHIFT)
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#define SM5502_REG_INTM1_LKR_MASK (0x1 << SM5502_REG_INTM1_LKR_SHIFT)
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#define SM5502_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT)
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#define SM5502_REG_INTM1_OCP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT)
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#define SM5502_REG_INTM1_OVP_OCP_DIS_MASK (0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT)
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#define SM5502_REG_INTM2_VBUS_DET_SHIFT 0
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#define SM5502_REG_INTM2_REV_ACCE_SHIFT 1
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#define SM5502_REG_INTM2_ADC_CHG_SHIFT 2
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#define SM5502_REG_INTM2_STUCK_KEY_SHIFT 3
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#define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT 4
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#define SM5502_REG_INTM2_MHL_SHIFT 5
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#define SM5502_REG_INTM2_VBUS_DET_MASK (0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT)
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#define SM5502_REG_INTM2_REV_ACCE_MASK (0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT)
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#define SM5502_REG_INTM2_ADC_CHG_MASK (0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT)
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#define SM5502_REG_INTM2_STUCK_KEY_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT)
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#define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
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#define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT)
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#define SM5502_REG_ADC_SHIFT 0
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#define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT)
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#define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT 4
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#define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK (0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT)
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#define TIMING_KEY_PRESS_100MS 0x0
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#define TIMING_KEY_PRESS_200MS 0x1
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#define TIMING_KEY_PRESS_300MS 0x2
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#define TIMING_KEY_PRESS_400MS 0x3
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#define TIMING_KEY_PRESS_500MS 0x4
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#define TIMING_KEY_PRESS_600MS 0x5
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#define TIMING_KEY_PRESS_700MS 0x6
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#define TIMING_KEY_PRESS_800MS 0x7
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#define TIMING_KEY_PRESS_900MS 0x8
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#define TIMING_KEY_PRESS_1000MS 0x9
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#define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT 0
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#define SM5502_REG_TIMING_SET1_ADC_DET_MASK (0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT)
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#define TIMING_ADC_DET_50MS 0x0
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#define TIMING_ADC_DET_100MS 0x1
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#define TIMING_ADC_DET_150MS 0x2
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#define TIMING_ADC_DET_200MS 0x3
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#define TIMING_ADC_DET_300MS 0x4
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#define TIMING_ADC_DET_400MS 0x5
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#define TIMING_ADC_DET_500MS 0x6
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#define TIMING_ADC_DET_600MS 0x7
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#define TIMING_ADC_DET_700MS 0x8
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#define TIMING_ADC_DET_800MS 0x9
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#define TIMING_ADC_DET_900MS 0xA
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#define TIMING_ADC_DET_1000MS 0xB
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#define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT 4
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#define SM5502_REG_TIMING_SET2_SW_WAIT_MASK (0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT)
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#define TIMING_SW_WAIT_10MS 0x0
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#define TIMING_SW_WAIT_30MS 0x1
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#define TIMING_SW_WAIT_50MS 0x2
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#define TIMING_SW_WAIT_70MS 0x3
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#define TIMING_SW_WAIT_90MS 0x4
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#define TIMING_SW_WAIT_110MS 0x5
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#define TIMING_SW_WAIT_130MS 0x6
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#define TIMING_SW_WAIT_150MS 0x7
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#define TIMING_SW_WAIT_170MS 0x8
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#define TIMING_SW_WAIT_190MS 0x9
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#define TIMING_SW_WAIT_210MS 0xA
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#define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT 0
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#define SM5502_REG_TIMING_SET2_LONG_KEY_MASK (0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT)
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#define TIMING_LONG_KEY_300MS 0x0
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#define TIMING_LONG_KEY_400MS 0x1
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#define TIMING_LONG_KEY_500MS 0x2
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#define TIMING_LONG_KEY_600MS 0x3
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#define TIMING_LONG_KEY_700MS 0x4
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#define TIMING_LONG_KEY_800MS 0x5
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#define TIMING_LONG_KEY_900MS 0x6
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#define TIMING_LONG_KEY_1000MS 0x7
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#define TIMING_LONG_KEY_1100MS 0x8
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#define TIMING_LONG_KEY_1200MS 0x9
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#define TIMING_LONG_KEY_1300MS 0xA
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#define TIMING_LONG_KEY_1400MS 0xB
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#define TIMING_LONG_KEY_1500MS 0xC
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT 0
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT 1
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#define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT 2
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#define SM5502_REG_DEV_TYPE1_UART_SHIFT 3
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#define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT 4
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#define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT 5
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#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT 6
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#define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT 7
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT)
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_SDP_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT)
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#define SM5502_REG_DEV_TYPE1_UART_MASK (0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT)
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#define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK (0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT)
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#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0
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#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1
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#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2
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#define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT 3
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#define SM5502_REG_DEV_TYPE2_PPD_SHIFT 4
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#define SM5502_REG_DEV_TYPE2_TTY_SHIFT 5
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#define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT 6
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#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT)
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#define SM5502_REG_DEV_TYPE2_PPD_MASK (0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT)
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#define SM5502_REG_DEV_TYPE2_TTY_MASK (0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT)
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#define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK (0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT)
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#define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT 0
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#define SM5502_REG_MANUAL_SW1_DP_SHIFT 2
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#define SM5502_REG_MANUAL_SW1_DM_SHIFT 5
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#define SM5502_REG_MANUAL_SW1_VBUSIN_MASK (0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT)
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#define SM5502_REG_MANUAL_SW1_DP_MASK (0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT)
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#define SM5502_REG_MANUAL_SW1_DM_MASK (0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT)
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#define VBUSIN_SWITCH_OPEN 0x0
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#define VBUSIN_SWITCH_VBUSOUT 0x1
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#define VBUSIN_SWITCH_MIC 0x2
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#define VBUSIN_SWITCH_VBUSOUT_WITH_USB 0x3
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#define DM_DP_CON_SWITCH_OPEN 0x0
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#define DM_DP_CON_SWITCH_USB 0x1
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#define DM_DP_CON_SWITCH_AUDIO 0x2
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#define DM_DP_CON_SWITCH_UART 0x3
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#define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define DM_DP_SWITCH_AUDIO ((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define SM5502_REG_RESET_MASK (0x1)
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/* SM5502 Interrupts */
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enum sm5502_irq {
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/* INT1 */
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SM5502_IRQ_INT1_ATTACH,
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SM5502_IRQ_INT1_DETACH,
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SM5502_IRQ_INT1_KP,
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SM5502_IRQ_INT1_LKP,
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SM5502_IRQ_INT1_LKR,
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SM5502_IRQ_INT1_OVP_EVENT,
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SM5502_IRQ_INT1_OCP_EVENT,
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SM5502_IRQ_INT1_OVP_OCP_DIS,
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/* INT2 */
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SM5502_IRQ_INT2_VBUS_DET,
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SM5502_IRQ_INT2_REV_ACCE,
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SM5502_IRQ_INT2_ADC_CHG,
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SM5502_IRQ_INT2_STUCK_KEY,
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SM5502_IRQ_INT2_STUCK_KEY_RCV,
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SM5502_IRQ_INT2_MHL,
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SM5502_IRQ_NUM,
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};
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#define SM5502_IRQ_INT1_ATTACH_MASK BIT(0)
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#define SM5502_IRQ_INT1_DETACH_MASK BIT(1)
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#define SM5502_IRQ_INT1_KP_MASK BIT(2)
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#define SM5502_IRQ_INT1_LKP_MASK BIT(3)
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#define SM5502_IRQ_INT1_LKR_MASK BIT(4)
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#define SM5502_IRQ_INT1_OVP_EVENT_MASK BIT(5)
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#define SM5502_IRQ_INT1_OCP_EVENT_MASK BIT(6)
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#define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK BIT(7)
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#define SM5502_IRQ_INT2_VBUS_DET_MASK BIT(0)
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#define SM5502_IRQ_INT2_REV_ACCE_MASK BIT(1)
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#define SM5502_IRQ_INT2_ADC_CHG_MASK BIT(2)
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#define SM5502_IRQ_INT2_STUCK_KEY_MASK BIT(3)
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#define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4)
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#define SM5502_IRQ_INT2_MHL_MASK BIT(5)
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#endif /* __LINUX_EXTCON_SM5502_H */
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