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46e2856b8e
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, the CPU frequency subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information. This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
174 lines
4.7 KiB
C
174 lines
4.7 KiB
C
/*
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* Copyright (C) 2016 Linaro.
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* Viresh Kumar <viresh.kumar@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "cpufreq-dt.h"
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/*
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* Machines for which the cpufreq device is *always* created, mostly used for
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* platforms using "operating-points" (V1) property.
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*/
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static const struct of_device_id whitelist[] __initconst = {
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{ .compatible = "allwinner,sun4i-a10", },
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{ .compatible = "allwinner,sun5i-a10s", },
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{ .compatible = "allwinner,sun5i-a13", },
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{ .compatible = "allwinner,sun5i-r8", },
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{ .compatible = "allwinner,sun6i-a31", },
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{ .compatible = "allwinner,sun6i-a31s", },
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{ .compatible = "allwinner,sun7i-a20", },
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{ .compatible = "allwinner,sun8i-a23", },
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{ .compatible = "allwinner,sun8i-a83t", },
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{ .compatible = "allwinner,sun8i-h3", },
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{ .compatible = "apm,xgene-shadowcat", },
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{ .compatible = "arm,integrator-ap", },
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{ .compatible = "arm,integrator-cp", },
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{ .compatible = "hisilicon,hi3660", },
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{ .compatible = "fsl,imx27", },
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{ .compatible = "fsl,imx51", },
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{ .compatible = "fsl,imx53", },
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{ .compatible = "fsl,imx7d", },
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{ .compatible = "marvell,berlin", },
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{ .compatible = "marvell,pxa250", },
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{ .compatible = "marvell,pxa270", },
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{ .compatible = "samsung,exynos3250", },
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{ .compatible = "samsung,exynos4210", },
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{ .compatible = "samsung,exynos5250", },
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#ifndef CONFIG_BL_SWITCHER
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{ .compatible = "samsung,exynos5800", },
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#endif
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{ .compatible = "renesas,emev2", },
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{ .compatible = "renesas,r7s72100", },
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{ .compatible = "renesas,r8a73a4", },
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{ .compatible = "renesas,r8a7740", },
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{ .compatible = "renesas,r8a7743", },
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{ .compatible = "renesas,r8a7745", },
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{ .compatible = "renesas,r8a7778", },
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{ .compatible = "renesas,r8a7779", },
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{ .compatible = "renesas,r8a7790", },
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{ .compatible = "renesas,r8a7791", },
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{ .compatible = "renesas,r8a7792", },
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{ .compatible = "renesas,r8a7793", },
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{ .compatible = "renesas,r8a7794", },
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{ .compatible = "renesas,sh73a0", },
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{ .compatible = "rockchip,rk2928", },
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{ .compatible = "rockchip,rk3036", },
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{ .compatible = "rockchip,rk3066a", },
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{ .compatible = "rockchip,rk3066b", },
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{ .compatible = "rockchip,rk3188", },
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{ .compatible = "rockchip,rk3228", },
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{ .compatible = "rockchip,rk3288", },
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{ .compatible = "rockchip,rk3328", },
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{ .compatible = "rockchip,rk3366", },
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{ .compatible = "rockchip,rk3368", },
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{ .compatible = "rockchip,rk3399", },
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{ .compatible = "st-ericsson,u8500", },
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{ .compatible = "st-ericsson,u8540", },
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{ .compatible = "st-ericsson,u9500", },
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{ .compatible = "st-ericsson,u9540", },
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{ .compatible = "ti,omap2", },
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{ .compatible = "ti,omap3", },
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{ .compatible = "ti,omap4", },
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{ .compatible = "ti,omap5", },
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{ .compatible = "xlnx,zynq-7000", },
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{ .compatible = "xlnx,zynqmp", },
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{ }
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};
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/*
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* Machines for which the cpufreq device is *not* created, mostly used for
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* platforms using "operating-points-v2" property.
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*/
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static const struct of_device_id blacklist[] __initconst = {
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{ .compatible = "calxeda,highbank", },
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{ .compatible = "calxeda,ecx-2000", },
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{ .compatible = "marvell,armadaxp", },
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{ .compatible = "mediatek,mt2701", },
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{ .compatible = "mediatek,mt2712", },
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{ .compatible = "mediatek,mt7622", },
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{ .compatible = "mediatek,mt7623", },
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{ .compatible = "mediatek,mt817x", },
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{ .compatible = "mediatek,mt8173", },
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{ .compatible = "mediatek,mt8176", },
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{ .compatible = "nvidia,tegra124", },
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{ .compatible = "qcom,apq8096", },
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{ .compatible = "qcom,msm8996", },
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{ .compatible = "st,stih407", },
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{ .compatible = "st,stih410", },
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{ .compatible = "sigma,tango4", },
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{ .compatible = "ti,am33xx", },
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{ .compatible = "ti,am43", },
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{ .compatible = "ti,dra7", },
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{ }
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};
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static bool __init cpu0_node_has_opp_v2_prop(void)
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{
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struct device_node *np = of_cpu_device_node_get(0);
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bool ret = false;
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if (of_get_property(np, "operating-points-v2", NULL))
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ret = true;
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of_node_put(np);
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return ret;
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}
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static int __init cpufreq_dt_platdev_init(void)
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{
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struct device_node *np = of_find_node_by_path("/");
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const struct of_device_id *match;
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const void *data = NULL;
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if (!np)
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return -ENODEV;
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match = of_match_node(whitelist, np);
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if (match) {
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data = match->data;
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goto create_pdev;
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}
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if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
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goto create_pdev;
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of_node_put(np);
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return -ENODEV;
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create_pdev:
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of_node_put(np);
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return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
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-1, data,
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sizeof(struct cpufreq_dt_platform_data)));
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}
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device_initcall(cpufreq_dt_platdev_init);
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