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This patch implements the basic framework of the driver for FPGA PCIe device which implements the Device Feature List (DFL) in its MMIO space. This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including both integrated (e.g. Intel Server Platform with In-package FPGA) and discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions. Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> Signed-off-by: Shiva Rao <shiva.rao@intel.com> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> Signed-off-by: Zhang Yi <yi.z.zhang@intel.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA Device Feature List (DFL) PCIe device
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Zhang Yi <Yi.Z.Zhang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/stddef.h>
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#include <linux/errno.h>
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#include <linux/aer.h>
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#define DRV_VERSION "0.8"
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#define DRV_NAME "dfl-pci"
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/* PCI Device ID */
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#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
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#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
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#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
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/* VF Device */
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#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
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#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
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#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
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static struct pci_device_id cci_pcie_id_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
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{0,}
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};
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MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
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static
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int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
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{
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int ret;
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ret = pcim_enable_device(pcidev);
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if (ret < 0) {
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dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
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return ret;
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}
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ret = pci_enable_pcie_error_reporting(pcidev);
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if (ret && ret != -EINVAL)
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dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
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pci_set_master(pcidev);
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if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
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ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
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if (ret)
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goto disable_error_report_exit;
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} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
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ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
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if (ret)
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goto disable_error_report_exit;
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} else {
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ret = -EIO;
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dev_err(&pcidev->dev, "No suitable DMA support available.\n");
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goto disable_error_report_exit;
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}
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/* TODO: create and add the platform device per feature list */
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return 0;
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disable_error_report_exit:
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pci_disable_pcie_error_reporting(pcidev);
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return ret;
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}
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static void cci_pci_remove(struct pci_dev *pcidev)
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{
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pci_disable_pcie_error_reporting(pcidev);
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}
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static struct pci_driver cci_pci_driver = {
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.name = DRV_NAME,
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.id_table = cci_pcie_id_tbl,
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.probe = cci_pci_probe,
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.remove = cci_pci_remove,
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};
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module_pci_driver(cci_pci_driver);
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MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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