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The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
293 lines
9.3 KiB
C
293 lines
9.3 KiB
C
/**
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* gadget.h - DesignWare USB3 DRD Gadget Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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* All rights reserved.
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DRIVERS_USB_DWC3_GADGET_H
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#define __DRIVERS_USB_DWC3_GADGET_H
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#include <linux/list.h>
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#include <linux/usb/gadget.h>
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#include "io.h"
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struct dwc3;
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#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
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#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
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/**
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* struct dwc3_gadget_ep_depcfg_param1 - DEPCMDPAR0 for DEPCFG command
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* @interrupt_number: self-explanatory
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* @reserved7_5: set to zero
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* @xfer_complete_enable: event generated when transfer completed
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* @xfer_in_progress_enable: event generated when transfer in progress
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* @xfer_not_ready_enable: event generated when transfer not read
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* @fifo_error_enable: generates events when FIFO Underrun (IN eps)
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* or FIFO Overrun (OUT) eps
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* @reserved_12: set to zero
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* @stream_event_enable: event generated on stream
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* @reserved14_15: set to zero
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* @binterval_m1: bInterval minus 1
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* @stream_capable: this EP is capable of handling streams
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* @ep_number: self-explanatory
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* @bulk_based: Set to ‘1’ if this isochronous endpoint represents a bulk
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* data stream that ignores the relationship of bus time to the
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* intervals programmed in TRBs.
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* @fifo_based: Set to ‘1’ if this isochronous endpoint represents a
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* FIFO-based data stream where TRBs have fixed values and are never
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* written back by the core.
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*/
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struct dwc3_gadget_ep_depcfg_param1 {
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u32 interrupt_number:5;
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u32 reserved7_5:3; /* set to zero */
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u32 xfer_complete_enable:1;
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u32 xfer_in_progress_enable:1;
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u32 xfer_not_ready_enable:1;
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u32 fifo_error_enable:1; /* IN-underrun, OUT-overrun */
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u32 reserved12:1; /* set to zero */
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u32 stream_event_enable:1;
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u32 reserved14_15:2;
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u32 binterval_m1:8; /* bInterval minus 1 */
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u32 stream_capable:1;
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u32 ep_number:5;
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u32 bulk_based:1;
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u32 fifo_based:1;
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} __packed;
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/**
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* struct dwc3_gadget_ep_depcfg_param0 - Parameter 0 for DEPCFG
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* @reserved0: set to zero
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* @ep_type: Endpoint Type (control, bulk, iso, interrupt)
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* @max_packet_size: max packet size in bytes
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* @reserved16_14: set to zero
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* @fifo_number: self-explanatory
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* @burst_size: burst size minus 1
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* @data_sequence_number: Must be 0 when an endpoint is initially configured
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* May be non-zero when an endpoint is configured after a power transition
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* that requires a save/restore.
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* @ignore_sequence_number: Set to ‘1’ to avoid resetting the sequence
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* number. This setting is used by software to modify the DEPEVTEN
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* event enable bits without modifying other endpoint settings.
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*/
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struct dwc3_gadget_ep_depcfg_param0 {
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u32 reserved0:1;
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u32 ep_type:2;
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u32 max_packet_size:11;
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u32 reserved16_14:3;
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u32 fifo_number:5;
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u32 burst_size:4;
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u32 data_sequence_number:5;
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u32 ignore_sequence_number:1;
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} __packed;
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/**
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* struct dwc3_gadget_ep_depxfercfg_param0 - Parameter 0 of DEPXFERCFG
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* @number_xfer_resources: Defines the number of Transfer Resources allocated
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* to this endpoint. This field must be set to 1.
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* @reserved16_31: set to zero;
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*/
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struct dwc3_gadget_ep_depxfercfg_param0 {
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u32 number_xfer_resources:16;
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u32 reserved16_31:16;
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} __packed;
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/**
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* struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
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* @transfer_desc_addr_low: Indicates the lower 32 bits of the external
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* memory's start address for the transfer descriptor. Because TRBs
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* must be aligned to a 16-byte boundary, the lower 4 bits of this
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* address must be 0.
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*/
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struct dwc3_gadget_ep_depstrtxfer_param1 {
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u32 transfer_desc_addr_low;
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} __packed;
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/**
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* struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
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* @transfer_desc_addr_high: Indicates the higher 32 bits of the external
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* memory’s start address for the transfer descriptor.
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*/
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struct dwc3_gadget_ep_depstrtxfer_param0 {
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u32 transfer_desc_addr_high;
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} __packed;
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struct dwc3_gadget_ep_cmd_params {
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union {
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u32 raw;
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} param2;
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union {
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u32 raw;
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struct dwc3_gadget_ep_depcfg_param1 depcfg;
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struct dwc3_gadget_ep_depstrtxfer_param1 depstrtxfer;
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} param1;
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union {
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u32 raw;
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struct dwc3_gadget_ep_depcfg_param0 depcfg;
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struct dwc3_gadget_ep_depxfercfg_param0 depxfercfg;
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struct dwc3_gadget_ep_depstrtxfer_param0 depstrtxfer;
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} param0;
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} __packed;
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/* -------------------------------------------------------------------------- */
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struct dwc3_request {
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struct usb_request request;
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struct list_head list;
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struct dwc3_ep *dep;
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u8 epnum;
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struct dwc3_trb_hw *trb;
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dma_addr_t trb_dma;
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unsigned direction:1;
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unsigned mapped:1;
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unsigned queued:1;
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};
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#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
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static inline struct dwc3_request *next_request(struct list_head *list)
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{
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if (list_empty(list))
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return NULL;
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return list_first_entry(list, struct dwc3_request, list);
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}
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static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
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{
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struct dwc3_ep *dep = req->dep;
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req->queued = true;
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list_move_tail(&req->list, &dep->req_queued);
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}
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#if defined(CONFIG_USB_GADGET_DWC3) || defined(CONFIG_USB_GADGET_DWC3_MODULE)
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int dwc3_gadget_init(struct dwc3 *dwc);
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void dwc3_gadget_exit(struct dwc3 *dwc);
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#else
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static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; }
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static inline void dwc3_gadget_exit(struct dwc3 *dwc) { }
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#endif
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void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
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int status);
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void dwc3_ep0_interrupt(struct dwc3 *dwc, const struct dwc3_event_depevt *event);
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void dwc3_ep0_out_start(struct dwc3 *dwc);
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
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gfp_t gfp_flags);
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int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
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int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
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unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
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void dwc3_map_buffer_to_dma(struct dwc3_request *req);
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void dwc3_unmap_buffer_from_dma(struct dwc3_request *req);
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/**
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* dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
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* @dwc: DesignWare USB3 Pointer
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* @number: DWC endpoint number
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*
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* Caller should take care of locking
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*/
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static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
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{
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u32 res_id;
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res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
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return DWC3_DEPCMD_GET_RSC_IDX(res_id);
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}
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/**
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* dwc3_gadget_event_string - returns event name
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* @event: the event code
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*/
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static inline const char *dwc3_gadget_event_string(u8 event)
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{
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switch (event) {
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case DWC3_DEVICE_EVENT_DISCONNECT:
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return "Disconnect";
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case DWC3_DEVICE_EVENT_RESET:
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return "Reset";
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case DWC3_DEVICE_EVENT_CONNECT_DONE:
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return "Connection Done";
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case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
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return "Link Status Change";
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case DWC3_DEVICE_EVENT_WAKEUP:
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return "WakeUp";
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case DWC3_DEVICE_EVENT_EOPF:
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return "End-Of-Frame";
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case DWC3_DEVICE_EVENT_SOF:
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return "Start-Of-Frame";
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case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
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return "Erratic Error";
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case DWC3_DEVICE_EVENT_CMD_CMPL:
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return "Command Complete";
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case DWC3_DEVICE_EVENT_OVERFLOW:
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return "Overflow";
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}
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return "UNKNOWN";
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}
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/**
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* dwc3_ep_event_string - returns event name
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* @event: then event code
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*/
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static inline const char *dwc3_ep_event_string(u8 event)
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{
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switch (event) {
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case DWC3_DEPEVT_XFERCOMPLETE:
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return "Transfer Complete";
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case DWC3_DEPEVT_XFERINPROGRESS:
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return "Transfer In-Progress";
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case DWC3_DEPEVT_XFERNOTREADY:
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return "Transfer Not Ready";
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case DWC3_DEPEVT_RXTXFIFOEVT:
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return "FIFO";
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case DWC3_DEPEVT_STREAMEVT:
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return "Stream";
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case DWC3_DEPEVT_EPCMDCMPLT:
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return "Endpoint Command Complete";
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}
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return "UNKNOWN";
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}
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#endif /* __DRIVERS_USB_DWC3_GADGET_H */
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