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On pre-A0 revisions of the mv78xx0 SoC, the third and fourth ethernet interface are not brought out to pins, but are internally cross-connected, so if we run on pre-A0 silicon, we'll force eth2 and eth3 to PHYless mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> |
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include/mach | ||
addr-map.c | ||
common.c | ||
common.h | ||
db78x00-bp-setup.c | ||
irq.c | ||
Kconfig | ||
Makefile | ||
Makefile.boot | ||
pcie.c |