mirror of
https://github.com/torvalds/linux.git
synced 2024-11-18 18:11:56 +00:00
8bd26e3a7e
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
108 lines
2.6 KiB
C
108 lines
2.6 KiB
C
/*
|
|
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
* Copyright 2011 Linaro Ltd.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/smp.h>
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/page.h>
|
|
#include <asm/smp_scu.h>
|
|
#include <asm/mach/map.h>
|
|
|
|
#include "common.h"
|
|
#include "hardware.h"
|
|
|
|
#define SCU_STANDBY_ENABLE (1 << 5)
|
|
|
|
u32 g_diag_reg;
|
|
static void __iomem *scu_base;
|
|
|
|
static struct map_desc scu_io_desc __initdata = {
|
|
/* .virtual and .pfn are run-time assigned */
|
|
.length = SZ_4K,
|
|
.type = MT_DEVICE,
|
|
};
|
|
|
|
void __init imx_scu_map_io(void)
|
|
{
|
|
unsigned long base;
|
|
|
|
/* Get SCU base */
|
|
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
|
|
|
|
scu_io_desc.virtual = IMX_IO_P2V(base);
|
|
scu_io_desc.pfn = __phys_to_pfn(base);
|
|
iotable_init(&scu_io_desc, 1);
|
|
|
|
scu_base = IMX_IO_ADDRESS(base);
|
|
}
|
|
|
|
void imx_scu_standby_enable(void)
|
|
{
|
|
u32 val = readl_relaxed(scu_base);
|
|
|
|
val |= SCU_STANDBY_ENABLE;
|
|
writel_relaxed(val, scu_base);
|
|
}
|
|
|
|
static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
{
|
|
imx_set_cpu_jump(cpu, v7_secondary_startup);
|
|
imx_enable_cpu(cpu, true);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Initialise the CPU possible map early - this describes the CPUs
|
|
* which may be present or become present in the system.
|
|
*/
|
|
static void __init imx_smp_init_cpus(void)
|
|
{
|
|
int i, ncores;
|
|
|
|
ncores = scu_get_core_count(scu_base);
|
|
|
|
for (i = ncores; i < NR_CPUS; i++)
|
|
set_cpu_possible(i, false);
|
|
}
|
|
|
|
void imx_smp_prepare(void)
|
|
{
|
|
scu_enable(scu_base);
|
|
}
|
|
|
|
static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
imx_smp_prepare();
|
|
|
|
/*
|
|
* The diagnostic register holds the errata bits. Mostly bootloader
|
|
* does not bring up secondary cores, so that when errata bits are set
|
|
* in bootloader, they are set only for boot cpu. But on a SMP
|
|
* configuration, it should be equally done on every single core.
|
|
* Read the register from boot cpu here, and will replicate it into
|
|
* secondary cores when booting them.
|
|
*/
|
|
asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
|
|
__cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));
|
|
outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));
|
|
}
|
|
|
|
struct smp_operations imx_smp_ops __initdata = {
|
|
.smp_init_cpus = imx_smp_init_cpus,
|
|
.smp_prepare_cpus = imx_smp_prepare_cpus,
|
|
.smp_boot_secondary = imx_boot_secondary,
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
.cpu_die = imx_cpu_die,
|
|
.cpu_kill = imx_cpu_kill,
|
|
#endif
|
|
};
|