Alex Deucher 6f0fd91947 drm/amdgpu: count fences from all uvd instances in idle handler ... Current multi-UVD hardware uses a single clock and power source so handle all instances in the idle handler. Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-05-18 16:08:20 -05:00
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drm	drm/amdgpu: count fences from all uvd instances in idle handler	2018-05-18 16:08:20 -05:00
host1x
ipu-v3	gpu: ipu-v3: prg: avoid possible array underflow	2018-03-15 17:52:08 +01:00
vga	vga_switcheroo: Let HDA autosuspend on mux change	2018-03-13 22:58:49 +01:00
Makefile