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4aebb79021
DRM_FORMAT_RGB888 is 24 bits per pixel and it would be natural to send it on the SPI bus using a 24 bits per word transfer. The problem with this is that not all SPI controllers support 24 bpw. Since DRM_FORMAT_RGB888 is stored in memory as little endian and the SPI bus is big endian we use 8 bpw to always get the same pixel format on the bus: b8g8r8. The MIPI DCS specification lists the standard commands that can be sent over the MIPI DBI interface. The set_address_mode (36h) command has one bit in the parameter that controls RGB/BGR order. This means that the controller can be configured to receive the pixel as BGR. RGB888 is rarely supported on these controllers but RGB666 is very common. All datasheets I have seen do at least support the pixel format option where each color is sent as one byte and the 6 MSB's are used. All this put together means that we can send each pixel as b8g8r8 and an RGB666 capable controller sees this as b6x2g6x2r6x2. v4: - s/emulation_format/pixel_format/ (Dmitry) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240604-panel-mipi-dbi-rgb666-v4-4-d7c2bcb9b78d@tronnes.org Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
260 lines
7.1 KiB
C
260 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* MIPI Display Bus Interface (DBI) LCD controller support
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*
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* Copyright 2016 Noralf Trønnes
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*/
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#ifndef __LINUX_MIPI_DBI_H
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#define __LINUX_MIPI_DBI_H
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#include <linux/mutex.h>
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#include <drm/drm_device.h>
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#include <drm/drm_simple_kms_helper.h>
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struct drm_format_conv_state;
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struct drm_rect;
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struct gpio_desc;
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struct iosys_map;
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struct regulator;
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struct spi_device;
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/**
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* struct mipi_dbi - MIPI DBI interface
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*/
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struct mipi_dbi {
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/**
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* @cmdlock: Command lock
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*/
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struct mutex cmdlock;
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/**
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* @command: Bus specific callback executing commands.
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*/
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int (*command)(struct mipi_dbi *dbi, u8 *cmd, u8 *param, size_t num);
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/**
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* @read_commands: Array of read commands terminated by a zero entry.
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* Reading is disabled if this is NULL.
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*/
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const u8 *read_commands;
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/**
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* @swap_bytes: Swap bytes in buffer before transfer
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*/
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bool swap_bytes;
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/**
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* @reset: Optional reset gpio
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*/
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struct gpio_desc *reset;
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/* Type C specific */
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/**
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* @spi: SPI device
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*/
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struct spi_device *spi;
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/**
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* @write_memory_bpw: Bits per word used on a MIPI_DCS_WRITE_MEMORY_START transfer
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*/
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unsigned int write_memory_bpw;
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/**
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* @dc: Optional D/C gpio.
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*/
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struct gpio_desc *dc;
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/**
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* @tx_buf9: Buffer used for Option 1 9-bit conversion
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*/
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void *tx_buf9;
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/**
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* @tx_buf9_len: Size of tx_buf9.
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*/
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size_t tx_buf9_len;
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};
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/**
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* struct mipi_dbi_dev - MIPI DBI device
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*/
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struct mipi_dbi_dev {
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/**
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* @drm: DRM device
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*/
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struct drm_device drm;
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/**
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* @pipe: Display pipe structure
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*/
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struct drm_simple_display_pipe pipe;
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/**
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* @connector: Connector
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*/
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struct drm_connector connector;
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/**
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* @mode: Fixed display mode
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*/
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struct drm_display_mode mode;
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/**
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* @pixel_format: Native pixel format (DRM_FORMAT\_\*)
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*/
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u32 pixel_format;
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/**
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* @tx_buf: Buffer used for transfer (copy clip rect area)
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*/
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u16 *tx_buf;
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/**
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* @rotation: initial rotation in degrees Counter Clock Wise
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*/
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unsigned int rotation;
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/**
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* @left_offset: Horizontal offset of the display relative to the
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* controller's driver array
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*/
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unsigned int left_offset;
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/**
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* @top_offset: Vertical offset of the display relative to the
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* controller's driver array
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*/
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unsigned int top_offset;
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/**
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* @backlight: backlight device (optional)
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*/
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struct backlight_device *backlight;
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/**
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* @regulator: power regulator (Vdd) (optional)
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*/
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struct regulator *regulator;
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/**
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* @io_regulator: I/O power regulator (Vddi) (optional)
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*/
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struct regulator *io_regulator;
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/**
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* @dbi: MIPI DBI interface
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*/
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struct mipi_dbi dbi;
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/**
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* @driver_private: Driver private data.
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* Necessary for drivers with private data since devm_drm_dev_alloc()
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* can't allocate structures that embed a structure which then again
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* embeds drm_device.
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*/
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void *driver_private;
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};
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static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm)
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{
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return container_of(drm, struct mipi_dbi_dev, drm);
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}
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int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
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struct gpio_desc *dc);
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int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
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const struct drm_simple_display_pipe_funcs *funcs,
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const uint32_t *formats, unsigned int format_count,
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const struct drm_display_mode *mode,
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unsigned int rotation, size_t tx_buf_size);
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int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
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const struct drm_simple_display_pipe_funcs *funcs,
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const struct drm_display_mode *mode, unsigned int rotation);
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enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
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const struct drm_display_mode *mode);
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void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *old_state);
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void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
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struct drm_crtc_state *crtc_state,
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struct drm_plane_state *plan_state);
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void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe);
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int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *plane_state);
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void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *plane_state);
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void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe);
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struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe);
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void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *plane_state);
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void mipi_dbi_hw_reset(struct mipi_dbi *dbi);
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bool mipi_dbi_display_is_on(struct mipi_dbi *dbi);
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int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev);
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int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev);
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u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len);
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int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
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u8 bpw, const void *buf, size_t len);
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int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val);
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int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len);
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int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
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size_t len);
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int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb,
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struct drm_rect *clip, bool swap,
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struct drm_format_conv_state *fmtcnv_state);
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/**
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* mipi_dbi_command - MIPI DCS command with optional parameter(s)
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* @dbi: MIPI DBI structure
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* @cmd: Command
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* @seq: Optional parameter(s)
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*
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* Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
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* get/read.
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*
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* Returns:
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* Zero on success, negative error code on failure.
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*/
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#define mipi_dbi_command(dbi, cmd, seq...) \
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({ \
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const u8 d[] = { seq }; \
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struct device *dev = &(dbi)->spi->dev; \
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int ret; \
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ret = mipi_dbi_command_stackbuf(dbi, cmd, d, ARRAY_SIZE(d)); \
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if (ret) \
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dev_err_ratelimited(dev, "error %d when sending command %#02x\n", ret, cmd); \
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ret; \
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})
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#ifdef CONFIG_DEBUG_FS
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void mipi_dbi_debugfs_init(struct drm_minor *minor);
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#else
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static inline void mipi_dbi_debugfs_init(struct drm_minor *minor) {}
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#endif
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/**
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* DRM_MIPI_DBI_SIMPLE_DISPLAY_PIPE_FUNCS - Initializes struct drm_simple_display_pipe_funcs
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* for MIPI-DBI devices
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* @enable_: Enable-callback implementation
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*
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* This macro initializes struct drm_simple_display_pipe_funcs with default
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* values for MIPI-DBI-based devices. The only callback that depends on the
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* hardware is @enable, for which the driver has to provide an implementation.
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* MIPI-based drivers are encouraged to use this macro for initialization.
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*/
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#define DRM_MIPI_DBI_SIMPLE_DISPLAY_PIPE_FUNCS(enable_) \
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.mode_valid = mipi_dbi_pipe_mode_valid, \
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.enable = (enable_), \
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.disable = mipi_dbi_pipe_disable, \
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.update = mipi_dbi_pipe_update, \
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.begin_fb_access = mipi_dbi_pipe_begin_fb_access, \
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.end_fb_access = mipi_dbi_pipe_end_fb_access, \
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.reset_plane = mipi_dbi_pipe_reset_plane, \
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.duplicate_plane_state = mipi_dbi_pipe_duplicate_plane_state, \
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.destroy_plane_state = mipi_dbi_pipe_destroy_plane_state
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#endif /* __LINUX_MIPI_DBI_H */
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