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e9f9c8262a
Commit 4972a80e16 (ARM: SAMSUNG: Add device tree support for pl330 dma
engine wrappers) introduced a new member 'dt_dmach_prop' in the struct
samsung_dma_info which is used to specify the dma channel number property
as obtained from the device tree. It also introduced a new dma request id
'DMACH_DT_PROP' to indicate that a device tree node property represting
the dma channel is available in 'struct samsung_dma_info'.
Add dma request id 'DMACH_DT_PROP' in s3c64xx dma channel id list in order
to maintain compatibility to the changes in the Samsung dma wrappper
operations.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C6400 - DMA support
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H __FILE__
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#define S3C_DMA_CHANNELS (16)
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/* see mach-s3c2410/dma.h for notes on dma channel numbers */
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/* Note, for the S3C64XX architecture we keep the DMACH_
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* defines in the order they are allocated to [S]DMA0/[S]DMA1
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* so that is easy to do DHACH_ -> DMA controller conversion
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*/
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enum dma_ch {
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/* DMA0/SDMA0 */
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DMACH_DT_PROP = -1, /* not yet supported, do not use */
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DMACH_UART0 = 0,
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DMACH_UART0_SRC2,
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DMACH_UART1,
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DMACH_UART1_SRC2,
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DMACH_UART2,
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DMACH_UART2_SRC2,
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DMACH_UART3,
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DMACH_UART3_SRC2,
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DMACH_PCM0_TX,
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DMACH_PCM0_RX,
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DMACH_I2S0_OUT,
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DMACH_I2S0_IN,
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DMACH_SPI0_TX,
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DMACH_SPI0_RX,
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DMACH_HSI_I2SV40_TX,
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DMACH_HSI_I2SV40_RX,
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/* DMA1/SDMA1 */
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DMACH_PCM1_TX = 16,
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DMACH_PCM1_RX,
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DMACH_I2S1_OUT,
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DMACH_I2S1_IN,
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DMACH_SPI1_TX,
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DMACH_SPI1_RX,
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DMACH_AC97_PCMOUT,
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DMACH_AC97_PCMIN,
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DMACH_AC97_MICIN,
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DMACH_PWM,
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DMACH_IRDA,
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DMACH_EXTERNAL,
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DMACH_RES1,
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DMACH_RES2,
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DMACH_SECURITY_RX, /* SDMA1 only */
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DMACH_SECURITY_TX, /* SDMA1 only */
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DMACH_MAX /* the end */
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};
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static inline bool samsung_dma_has_circular(void)
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{
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return true;
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}
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static inline bool samsung_dma_is_dmadev(void)
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{
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return false;
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}
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#define S3C2410_DMAF_CIRCULAR (1 << 0)
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#include <plat/dma.h>
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#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
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struct s3c64xx_dma_buff;
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/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
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* @next: Pointer to next buffer in queue or ring.
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* @pw: Client provided identifier
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* @lli: Pointer to hardware descriptor this buffer is associated with.
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* @lli_dma: Hardare address of the descriptor.
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*/
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struct s3c64xx_dma_buff {
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struct s3c64xx_dma_buff *next;
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void *pw;
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struct pl080s_lli *lli;
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dma_addr_t lli_dma;
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};
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struct s3c64xx_dmac;
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struct s3c2410_dma_chan {
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unsigned char number; /* number of this dma channel */
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unsigned char in_use; /* channel allocated */
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unsigned char bit; /* bit for enable/disable/etc */
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unsigned char hw_width;
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unsigned char peripheral;
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unsigned int flags;
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enum dma_data_direction source;
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dma_addr_t dev_addr;
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struct s3c2410_dma_client *client;
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struct s3c64xx_dmac *dmac; /* pointer to controller */
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void __iomem *regs;
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/* cdriver callbacks */
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s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
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s3c2410_dma_opfn_t op_fn; /* channel op callback */
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/* buffer list and information */
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struct s3c64xx_dma_buff *curr; /* current dma buffer */
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struct s3c64xx_dma_buff *next; /* next buffer to load */
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struct s3c64xx_dma_buff *end; /* end of queue */
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/* note, when channel is running in circular mode, curr is the
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* first buffer enqueued, end is the last and curr is where the
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* last buffer-done event is set-at. The buffers are not freed
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* and the last buffer hardware descriptor points back to the
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* first.
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*/
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};
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#include <plat/dma-core.h>
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#endif /* __ASM_ARCH_IRQ_H */
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