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ea31fd4330
This patch adds suspend-to-ram support for S5PV210. Note. This patch is confirmed on SMDKV210 and SMDKC110 board. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
171 lines
4.3 KiB
ArmAsm
171 lines
4.3 KiB
ArmAsm
/* linux/arch/arm/plat-s5p/sleep.S
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV210 power Manager (Suspend-To-RAM) support
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* Based on S3C2410 sleep code by:
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* Ben Dooks, (c) 2004 Simtec Electronics
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*
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* Based on PXA/SA1100 sleep code by:
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* Nicolas Pitre, (c) 2002 Monta Vista Software Inc
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* Cliff Brake, (c) 2001
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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.text
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/* s3c_cpu_save
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*
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* entry:
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* r0 = save address (virtual addr of s3c_sleep_save_phys)
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*/
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ENTRY(s3c_cpu_save)
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stmfd sp!, { r3 - r12, lr }
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
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mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
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stmia r0, { r3 - r13 }
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bl s3c_pm_cb_flushcache
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ldr r0, =pm_cpu_sleep
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ldr r0, [ r0 ]
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mov pc, r0
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resume_with_mmu:
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/*
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* After MMU is turned on, restore the previous MMU table.
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*/
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ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
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add r4, r4, r9
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str r12, [r4]
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ldmfd sp!, { r3 - r12, pc }
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.ltorg
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.data
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.global s3c_sleep_save_phys
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s3c_sleep_save_phys:
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.word 0
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/* sleep magic, to allow the bootloader to check for an valid
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* image to resume to. Must be the first word before the
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* s3c_cpu_resume entry.
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*/
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.word 0x2bedf00d
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/* s3c_cpu_resume
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*
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* resume code entry for bootloader to call
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*
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* we must put this code here in the data segment as we have no
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* other way of restoring the stack pointer after sleep, and we
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* must not write to the code segment (code is read-only)
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*/
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ENTRY(s3c_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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msr cpsr_c, r0
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
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ldr r0, s3c_sleep_save_phys @ address of restore block
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ldmia r0, { r3 - r13 }
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
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mov r0, #0 @ restore copro access
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
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mcr p15, 0, r0, c7, c5, 4
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mcr p15, 0, r12, c10, c2, 0 @ write PRRR
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mcr p15, 0, r3, c10, c2, 1 @ write NMRR
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/*
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* In Cortex-A8, when MMU is turned on, the pipeline is flushed.
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* And there are no valid entries in the MMU table at this point.
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* So before turning on the MMU, the MMU entry for the DRAM address
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* range is added. After the MMU is turned on, the other entries
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* in the MMU table will be restored.
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*/
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/* r6 = Translation Table BASE0 */
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mov r4, r6
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mov r4, r4, LSR #14
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mov r4, r4, LSL #14
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/* Load address for adding to MMU table list */
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ldr r11, =0xE010F000 @ INFORM0 reg.
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ldr r10, [r11, #0]
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mov r10, r10, LSR #18
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bic r10, r10, #0x3
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orr r4, r4, r10
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/* Calculate MMU table entry */
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mov r10, r10, LSL #18
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ldr r5, =0x40E
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orr r10, r10, r5
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/* Back up originally data */
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ldr r12, [r4]
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/* Add calculated MMU table entry into MMU table list */
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str r10, [r4]
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ldr r2, =resume_with_mmu
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mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
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nop
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nop
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nop
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nop
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nop @ second-to-last before mmu
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mov pc, r2 @ go back to virtual address
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.ltorg
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