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4d07a05397
The latency is calculated by dividing the flit size over the bandwidth. Add support to retrieve the flit size for the CXL switch device and calculate the latency of the PCIe link. Cache the latency number with cxl_dport. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/170319621931.2212653.6800240203604822886.stgit@djiang5-mobl3 Signed-off-by: Dan Williams <dan.j.williams@intel.com>
110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_PCI_H__
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#define __CXL_PCI_H__
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#include <linux/pci.h>
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#include "cxl.h"
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#define CXL_MEMORY_PROGIF 0x10
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/*
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* See section 8.1 Configuration Space Registers in the CXL 2.0
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* Specification. Names are taken straight from the specification with "CXL" and
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* "DVSEC" redundancies removed. When obvious, abbreviations may be used.
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*/
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#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
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#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
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/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
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#define CXL_DVSEC_PCIE_DEVICE 0
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#define CXL_DVSEC_CAP_OFFSET 0xA
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#define CXL_DVSEC_MEM_CAPABLE BIT(2)
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#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4)
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#define CXL_DVSEC_CTRL_OFFSET 0xC
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#define CXL_DVSEC_MEM_ENABLE BIT(2)
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#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
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#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
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#define CXL_DVSEC_MEM_INFO_VALID BIT(0)
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#define CXL_DVSEC_MEM_ACTIVE BIT(1)
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#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28)
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#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
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#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
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#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28)
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#define CXL_DVSEC_RANGE_MAX 2
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/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
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#define CXL_DVSEC_FUNCTION_MAP 2
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/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
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#define CXL_DVSEC_PORT_EXTENSIONS 3
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/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
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#define CXL_DVSEC_PORT_GPF 4
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/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
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#define CXL_DVSEC_DEVICE_GPF 5
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/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
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#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7
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/* CXL 2.0 8.1.9: Register Locator DVSEC */
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#define CXL_DVSEC_REG_LOCATOR 8
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#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
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#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16)
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/*
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* NOTE: Currently all the functions which are enabled for CXL require their
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* vectors to be in the first 16. Use this as the default max.
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*/
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#define CXL_PCI_DEFAULT_MAX_VECTORS 16
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/* Register Block Identifier (RBI) */
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enum cxl_regloc_type {
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CXL_REGLOC_RBI_EMPTY = 0,
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CXL_REGLOC_RBI_COMPONENT,
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CXL_REGLOC_RBI_VIRT,
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CXL_REGLOC_RBI_MEMDEV,
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CXL_REGLOC_RBI_PMU,
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CXL_REGLOC_RBI_TYPES
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};
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struct cdat_header {
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__le32 length;
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u8 revision;
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u8 checksum;
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u8 reserved[6];
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__le32 sequence;
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} __packed;
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struct cdat_entry_header {
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u8 type;
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u8 reserved;
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__le16 length;
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} __packed;
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/*
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* CXL v3.0 6.2.3 Table 6-4
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* The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
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* mode, otherwise it's 68B flits mode.
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*/
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static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
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{
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u16 lnksta2;
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2);
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return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
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}
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int devm_cxl_port_enumerate_dports(struct cxl_port *port);
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struct cxl_dev_state;
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int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
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struct cxl_endpoint_dvsec_info *info);
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void read_cdat_data(struct cxl_port *port);
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void cxl_cor_error_detected(struct pci_dev *pdev);
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pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
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pci_channel_state_t state);
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#endif /* __CXL_PCI_H__ */
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