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5a2f883124
Universe II datasheet defines following address space values for LM_CTL[16:18] 000=A16 001=A24 010=A32 011,100,101=Reserved 110=User1 111=User2 Mask 5<<16 is not the right one for matching [16:18], instead we should use 7<<16. Signed-off-by: Dmitry Kalinkin <dmitry.kalinkin@gmail.com> Cc: Igor Alekseev <igor.alekseev@itep.ru> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
583 lines
16 KiB
C
583 lines
16 KiB
C
/*
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* ca91c042.h
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*
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* Support for the Tundra Universe 1 and Universe II VME bridge chips
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*
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* Author: Tom Armistead
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* Updated by Ajit Prem
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* Copyright 2004 Motorola Inc.
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*
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* Further updated by Martyn Welch <martyn.welch@ge.com>
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* Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
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*
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* Derived from ca91c042.h by Michael Wyrick
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _CA91CX42_H
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#define _CA91CX42_H
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#ifndef PCI_VENDOR_ID_TUNDRA
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#define PCI_VENDOR_ID_TUNDRA 0x10e3
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#endif
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#ifndef PCI_DEVICE_ID_TUNDRA_CA91C142
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#define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
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#endif
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/*
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* Define the number of each that the CA91C142 supports.
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*/
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#define CA91C142_MAX_MASTER 8 /* Max Master Windows */
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#define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */
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#define CA91C142_MAX_DMA 1 /* Max DMA Controllers */
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#define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */
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/* Structure used to hold driver specific information */
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struct ca91cx42_driver {
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void __iomem *base; /* Base Address of device registers */
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wait_queue_head_t dma_queue;
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wait_queue_head_t iack_queue;
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wait_queue_head_t mbox_queue;
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void (*lm_callback[4])(int); /* Called in interrupt handler */
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void *crcsr_kernel;
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dma_addr_t crcsr_bus;
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struct mutex vme_rmw; /* Only one RMW cycle at a time */
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struct mutex vme_int; /*
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* Only one VME interrupt can be
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* generated at a time, provide locking
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*/
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};
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/* See Page 2-77 in the Universe User Manual */
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struct ca91cx42_dma_descriptor {
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unsigned int dctl; /* DMA Control */
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unsigned int dtbc; /* Transfer Byte Count */
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unsigned int dla; /* PCI Address */
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unsigned int res1; /* Reserved */
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unsigned int dva; /* Vme Address */
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unsigned int res2; /* Reserved */
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unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
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unsigned int res3; /* Reserved */
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};
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struct ca91cx42_dma_entry {
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struct ca91cx42_dma_descriptor descriptor;
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struct list_head list;
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};
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/* Universe Register Offsets */
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/* general PCI configuration registers */
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#define CA91CX42_PCI_ID 0x000
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#define CA91CX42_PCI_CSR 0x004
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#define CA91CX42_PCI_CLASS 0x008
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#define CA91CX42_PCI_MISC0 0x00C
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#define CA91CX42_PCI_BS 0x010
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#define CA91CX42_PCI_MISC1 0x03C
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#define LSI0_CTL 0x0100
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#define LSI0_BS 0x0104
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#define LSI0_BD 0x0108
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#define LSI0_TO 0x010C
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#define LSI1_CTL 0x0114
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#define LSI1_BS 0x0118
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#define LSI1_BD 0x011C
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#define LSI1_TO 0x0120
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#define LSI2_CTL 0x0128
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#define LSI2_BS 0x012C
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#define LSI2_BD 0x0130
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#define LSI2_TO 0x0134
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#define LSI3_CTL 0x013C
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#define LSI3_BS 0x0140
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#define LSI3_BD 0x0144
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#define LSI3_TO 0x0148
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#define LSI4_CTL 0x01A0
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#define LSI4_BS 0x01A4
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#define LSI4_BD 0x01A8
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#define LSI4_TO 0x01AC
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#define LSI5_CTL 0x01B4
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#define LSI5_BS 0x01B8
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#define LSI5_BD 0x01BC
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#define LSI5_TO 0x01C0
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#define LSI6_CTL 0x01C8
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#define LSI6_BS 0x01CC
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#define LSI6_BD 0x01D0
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#define LSI6_TO 0x01D4
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#define LSI7_CTL 0x01DC
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#define LSI7_BS 0x01E0
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#define LSI7_BD 0x01E4
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#define LSI7_TO 0x01E8
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static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL,
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LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL };
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static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS,
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LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS };
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static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD,
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LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD };
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static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO,
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LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO };
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#define SCYC_CTL 0x0170
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#define SCYC_ADDR 0x0174
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#define SCYC_EN 0x0178
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#define SCYC_CMP 0x017C
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#define SCYC_SWP 0x0180
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#define LMISC 0x0184
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#define SLSI 0x0188
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#define L_CMDERR 0x018C
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#define LAERR 0x0190
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#define DCTL 0x0200
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#define DTBC 0x0204
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#define DLA 0x0208
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#define DVA 0x0210
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#define DCPP 0x0218
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#define DGCS 0x0220
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#define D_LLUE 0x0224
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#define LINT_EN 0x0300
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#define LINT_STAT 0x0304
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#define LINT_MAP0 0x0308
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#define LINT_MAP1 0x030C
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#define VINT_EN 0x0310
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#define VINT_STAT 0x0314
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#define VINT_MAP0 0x0318
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#define VINT_MAP1 0x031C
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#define STATID 0x0320
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#define V1_STATID 0x0324
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#define V2_STATID 0x0328
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#define V3_STATID 0x032C
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#define V4_STATID 0x0330
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#define V5_STATID 0x0334
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#define V6_STATID 0x0338
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#define V7_STATID 0x033C
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static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID,
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V4_STATID, V5_STATID, V6_STATID,
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V7_STATID };
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#define LINT_MAP2 0x0340
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#define VINT_MAP2 0x0344
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#define MBOX0 0x0348
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#define MBOX1 0x034C
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#define MBOX2 0x0350
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#define MBOX3 0x0354
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#define SEMA0 0x0358
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#define SEMA1 0x035C
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#define MAST_CTL 0x0400
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#define MISC_CTL 0x0404
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#define MISC_STAT 0x0408
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#define USER_AM 0x040C
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#define VSI0_CTL 0x0F00
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#define VSI0_BS 0x0F04
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#define VSI0_BD 0x0F08
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#define VSI0_TO 0x0F0C
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#define VSI1_CTL 0x0F14
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#define VSI1_BS 0x0F18
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#define VSI1_BD 0x0F1C
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#define VSI1_TO 0x0F20
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#define VSI2_CTL 0x0F28
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#define VSI2_BS 0x0F2C
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#define VSI2_BD 0x0F30
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#define VSI2_TO 0x0F34
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#define VSI3_CTL 0x0F3C
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#define VSI3_BS 0x0F40
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#define VSI3_BD 0x0F44
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#define VSI3_TO 0x0F48
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#define LM_CTL 0x0F64
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#define LM_BS 0x0F68
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#define VRAI_CTL 0x0F70
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#define VRAI_BS 0x0F74
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#define VCSR_CTL 0x0F80
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#define VCSR_TO 0x0F84
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#define V_AMERR 0x0F88
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#define VAERR 0x0F8C
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#define VSI4_CTL 0x0F90
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#define VSI4_BS 0x0F94
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#define VSI4_BD 0x0F98
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#define VSI4_TO 0x0F9C
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#define VSI5_CTL 0x0FA4
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#define VSI5_BS 0x0FA8
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#define VSI5_BD 0x0FAC
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#define VSI5_TO 0x0FB0
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#define VSI6_CTL 0x0FB8
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#define VSI6_BS 0x0FBC
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#define VSI6_BD 0x0FC0
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#define VSI6_TO 0x0FC4
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#define VSI7_CTL 0x0FCC
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#define VSI7_BS 0x0FD0
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#define VSI7_BD 0x0FD4
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#define VSI7_TO 0x0FD8
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static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
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VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL };
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static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS,
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VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS };
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static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD,
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VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD };
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static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO,
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VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO };
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#define VCSR_CLR 0x0FF4
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#define VCSR_SET 0x0FF8
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#define VCSR_BS 0x0FFC
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/*
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* PCI Class Register
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* offset 008
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*/
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#define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000
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#define CA91CX42_OF_PCI_CLASS_BASE 24
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#define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000
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#define CA91CX42_OF_PCI_CLASS_SUB 16
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#define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00
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#define CA91CX42_OF_PCI_CLASS_PROG 8
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#define CA91CX42_BM_PCI_CLASS_RID 0x000000FF
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#define CA91CX42_OF_PCI_CLASS_RID 0
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#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0
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#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1
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/*
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* PCI Misc Register
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* offset 00C
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*/
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#define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000
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#define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000
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#define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000
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#define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000
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#define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000
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#define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00
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#define CA91CX42_OF_PCI_MISC0_LTIMER 8
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/*
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* LSI Control Register
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* offset 100
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*/
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#define CA91CX42_LSI_CTL_EN (1<<31)
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#define CA91CX42_LSI_CTL_PWEN (1<<30)
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#define CA91CX42_LSI_CTL_VDW_M (3<<22)
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#define CA91CX42_LSI_CTL_VDW_D8 0
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#define CA91CX42_LSI_CTL_VDW_D16 (1<<22)
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#define CA91CX42_LSI_CTL_VDW_D32 (1<<23)
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#define CA91CX42_LSI_CTL_VDW_D64 (3<<22)
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#define CA91CX42_LSI_CTL_VAS_M (7<<16)
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#define CA91CX42_LSI_CTL_VAS_A16 0
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#define CA91CX42_LSI_CTL_VAS_A24 (1<<16)
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#define CA91CX42_LSI_CTL_VAS_A32 (1<<17)
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#define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16)
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#define CA91CX42_LSI_CTL_VAS_USER1 (3<<17)
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#define CA91CX42_LSI_CTL_VAS_USER2 (7<<16)
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#define CA91CX42_LSI_CTL_PGM_M (1<<14)
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#define CA91CX42_LSI_CTL_PGM_DATA 0
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#define CA91CX42_LSI_CTL_PGM_PGM (1<<14)
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#define CA91CX42_LSI_CTL_SUPER_M (1<<12)
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#define CA91CX42_LSI_CTL_SUPER_NPRIV 0
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#define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12)
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#define CA91CX42_LSI_CTL_VCT_M (1<<8)
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#define CA91CX42_LSI_CTL_VCT_BLT (1<<8)
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#define CA91CX42_LSI_CTL_VCT_MBLT (1<<8)
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#define CA91CX42_LSI_CTL_LAS (1<<0)
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/*
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* SCYC_CTL Register
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* offset 178
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*/
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#define CA91CX42_SCYC_CTL_LAS_PCIMEM 0
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#define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2)
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#define CA91CX42_SCYC_CTL_CYC_M (3<<0)
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#define CA91CX42_SCYC_CTL_CYC_RMW (1<<0)
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#define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1)
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/*
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* LMISC Register
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* offset 184
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*/
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#define CA91CX42_BM_LMISC_CRT 0xF0000000
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#define CA91CX42_OF_LMISC_CRT 28
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#define CA91CX42_BM_LMISC_CWT 0x0F000000
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#define CA91CX42_OF_LMISC_CWT 24
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/*
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* SLSI Register
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* offset 188
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*/
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#define CA91CX42_BM_SLSI_EN 0x80000000
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#define CA91CX42_BM_SLSI_PWEN 0x40000000
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#define CA91CX42_BM_SLSI_VDW 0x00F00000
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#define CA91CX42_OF_SLSI_VDW 20
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#define CA91CX42_BM_SLSI_PGM 0x0000F000
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#define CA91CX42_OF_SLSI_PGM 12
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#define CA91CX42_BM_SLSI_SUPER 0x00000F00
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#define CA91CX42_OF_SLSI_SUPER 8
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#define CA91CX42_BM_SLSI_BS 0x000000F6
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#define CA91CX42_OF_SLSI_BS 2
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#define CA91CX42_BM_SLSI_LAS 0x00000003
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#define CA91CX42_OF_SLSI_LAS 0
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#define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000
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/*
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* DCTL Register
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* offset 200
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*/
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#define CA91CX42_DCTL_L2V (1<<31)
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#define CA91CX42_DCTL_VDW_M (3<<22)
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#define CA91CX42_DCTL_VDW_D8 0
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#define CA91CX42_DCTL_VDW_D16 (1<<22)
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#define CA91CX42_DCTL_VDW_D32 (1<<23)
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#define CA91CX42_DCTL_VDW_D64 (3<<22)
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#define CA91CX42_DCTL_VAS_M (7<<16)
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#define CA91CX42_DCTL_VAS_A16 0
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#define CA91CX42_DCTL_VAS_A24 (1<<16)
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#define CA91CX42_DCTL_VAS_A32 (1<<17)
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#define CA91CX42_DCTL_VAS_USER1 (3<<17)
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#define CA91CX42_DCTL_VAS_USER2 (7<<16)
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#define CA91CX42_DCTL_PGM_M (1<<14)
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#define CA91CX42_DCTL_PGM_DATA 0
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#define CA91CX42_DCTL_PGM_PGM (1<<14)
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#define CA91CX42_DCTL_SUPER_M (1<<12)
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#define CA91CX42_DCTL_SUPER_NPRIV 0
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#define CA91CX42_DCTL_SUPER_SUPR (1<<12)
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#define CA91CX42_DCTL_VCT_M (1<<8)
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#define CA91CX42_DCTL_VCT_BLT (1<<8)
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#define CA91CX42_DCTL_LD64EN (1<<7)
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/*
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* DCPP Register
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* offset 218
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*/
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#define CA91CX42_DCPP_M 0xf
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#define CA91CX42_DCPP_NULL (1<<0)
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/*
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* DMA General Control/Status Register (DGCS)
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* offset 220
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*/
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#define CA91CX42_DGCS_GO (1<<31)
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#define CA91CX42_DGCS_STOP_REQ (1<<30)
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#define CA91CX42_DGCS_HALT_REQ (1<<29)
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#define CA91CX42_DGCS_CHAIN (1<<27)
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#define CA91CX42_DGCS_VON_M (7<<20)
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#define CA91CX42_DGCS_VOFF_M (0xf<<16)
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#define CA91CX42_DGCS_ACT (1<<15)
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#define CA91CX42_DGCS_STOP (1<<14)
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#define CA91CX42_DGCS_HALT (1<<13)
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#define CA91CX42_DGCS_DONE (1<<11)
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#define CA91CX42_DGCS_LERR (1<<10)
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#define CA91CX42_DGCS_VERR (1<<9)
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#define CA91CX42_DGCS_PERR (1<<8)
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#define CA91CX42_DGCS_INT_STOP (1<<6)
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#define CA91CX42_DGCS_INT_HALT (1<<5)
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#define CA91CX42_DGCS_INT_DONE (1<<3)
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#define CA91CX42_DGCS_INT_LERR (1<<2)
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#define CA91CX42_DGCS_INT_VERR (1<<1)
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#define CA91CX42_DGCS_INT_PERR (1<<0)
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/*
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* PCI Interrupt Enable Register
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* offset 300
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*/
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#define CA91CX42_LINT_LM3 0x00800000
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#define CA91CX42_LINT_LM2 0x00400000
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#define CA91CX42_LINT_LM1 0x00200000
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#define CA91CX42_LINT_LM0 0x00100000
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#define CA91CX42_LINT_MBOX3 0x00080000
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#define CA91CX42_LINT_MBOX2 0x00040000
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#define CA91CX42_LINT_MBOX1 0x00020000
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#define CA91CX42_LINT_MBOX0 0x00010000
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#define CA91CX42_LINT_ACFAIL 0x00008000
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#define CA91CX42_LINT_SYSFAIL 0x00004000
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#define CA91CX42_LINT_SW_INT 0x00002000
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#define CA91CX42_LINT_SW_IACK 0x00001000
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#define CA91CX42_LINT_VERR 0x00000400
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#define CA91CX42_LINT_LERR 0x00000200
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#define CA91CX42_LINT_DMA 0x00000100
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#define CA91CX42_LINT_VIRQ7 0x00000080
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#define CA91CX42_LINT_VIRQ6 0x00000040
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#define CA91CX42_LINT_VIRQ5 0x00000020
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#define CA91CX42_LINT_VIRQ4 0x00000010
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#define CA91CX42_LINT_VIRQ3 0x00000008
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#define CA91CX42_LINT_VIRQ2 0x00000004
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#define CA91CX42_LINT_VIRQ1 0x00000002
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#define CA91CX42_LINT_VOWN 0x00000001
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static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1,
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CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3,
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CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5,
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CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 };
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#define CA91CX42_LINT_MBOX 0x000F0000
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static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1,
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CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 };
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/*
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* MAST_CTL Register
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* offset 400
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*/
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#define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000
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#define CA91CX42_OF_MAST_CTL_MAXRTRY 28
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#define CA91CX42_BM_MAST_CTL_PWON 0x0F000000
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#define CA91CX42_OF_MAST_CTL_PWON 24
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#define CA91CX42_BM_MAST_CTL_VRL 0x00C00000
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#define CA91CX42_OF_MAST_CTL_VRL 22
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#define CA91CX42_BM_MAST_CTL_VRM 0x00200000
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#define CA91CX42_BM_MAST_CTL_VREL 0x00100000
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#define CA91CX42_BM_MAST_CTL_VOWN 0x00080000
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#define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000
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#define CA91CX42_BM_MAST_CTL_PABS 0x00001000
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#define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F
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#define CA91CX42_OF_MAST_CTL_BUS_NO 0
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/*
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* MISC_CTL Register
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* offset 404
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*/
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#define CA91CX42_MISC_CTL_VBTO 0xF0000000
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#define CA91CX42_MISC_CTL_VARB 0x04000000
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#define CA91CX42_MISC_CTL_VARBTO 0x03000000
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#define CA91CX42_MISC_CTL_SW_LRST 0x00800000
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#define CA91CX42_MISC_CTL_SW_SRST 0x00400000
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#define CA91CX42_MISC_CTL_BI 0x00100000
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#define CA91CX42_MISC_CTL_ENGBI 0x00080000
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#define CA91CX42_MISC_CTL_RESCIND 0x00040000
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#define CA91CX42_MISC_CTL_SYSCON 0x00020000
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#define CA91CX42_MISC_CTL_V64AUTO 0x00010000
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#define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF
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#define CA91CX42_OF_MISC_CTL_VARBTO 24
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#define CA91CX42_OF_MISC_CTL_VBTO 28
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/*
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* MISC_STAT Register
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* offset 408
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*/
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#define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000
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#define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000
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#define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000
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#define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000
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#define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000
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#define CA91CX42_BM_MISC_STAT_TXFE 0x00040000
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#define CA91CX42_BM_MISC_STAT_RXFE 0x00020000
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#define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00
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#define CA91CX42_OF_MISC_STAT_DY4AUTOID 8
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/*
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* VSI Control Register
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* offset F00
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*/
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#define CA91CX42_VSI_CTL_EN (1<<31)
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#define CA91CX42_VSI_CTL_PWEN (1<<30)
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#define CA91CX42_VSI_CTL_PREN (1<<29)
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#define CA91CX42_VSI_CTL_PGM_M (3<<22)
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#define CA91CX42_VSI_CTL_PGM_DATA (1<<22)
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#define CA91CX42_VSI_CTL_PGM_PGM (1<<23)
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#define CA91CX42_VSI_CTL_SUPER_M (3<<20)
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#define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20)
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#define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21)
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#define CA91CX42_VSI_CTL_VAS_M (7<<16)
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#define CA91CX42_VSI_CTL_VAS_A16 0
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#define CA91CX42_VSI_CTL_VAS_A24 (1<<16)
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#define CA91CX42_VSI_CTL_VAS_A32 (1<<17)
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#define CA91CX42_VSI_CTL_VAS_USER1 (3<<17)
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#define CA91CX42_VSI_CTL_VAS_USER2 (7<<16)
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#define CA91CX42_VSI_CTL_LD64EN (1<<7)
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#define CA91CX42_VSI_CTL_LLRMW (1<<6)
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#define CA91CX42_VSI_CTL_LAS_M (3<<0)
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#define CA91CX42_VSI_CTL_LAS_PCI_MS 0
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#define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0)
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#define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1)
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/* LM_CTL Register
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* offset F64
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*/
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#define CA91CX42_LM_CTL_EN (1<<31)
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#define CA91CX42_LM_CTL_PGM (1<<23)
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#define CA91CX42_LM_CTL_DATA (1<<22)
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#define CA91CX42_LM_CTL_SUPR (1<<21)
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#define CA91CX42_LM_CTL_NPRIV (1<<20)
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#define CA91CX42_LM_CTL_AS_M (7<<16)
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#define CA91CX42_LM_CTL_AS_A16 0
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#define CA91CX42_LM_CTL_AS_A24 (1<<16)
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#define CA91CX42_LM_CTL_AS_A32 (1<<17)
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/*
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* VRAI_CTL Register
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* offset F70
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*/
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#define CA91CX42_BM_VRAI_CTL_EN 0x80000000
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#define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000
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#define CA91CX42_OF_VRAI_CTL_PGM 22
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#define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000
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#define CA91CX42_OF_VRAI_CTL_SUPER 20
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#define CA91CX42_BM_VRAI_CTL_VAS 0x00030000
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#define CA91CX42_OF_VRAI_CTL_VAS 16
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|
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/* VCSR_CTL Register
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* offset F80
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*/
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#define CA91CX42_VCSR_CTL_EN (1<<31)
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#define CA91CX42_VCSR_CTL_LAS_M (3<<0)
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#define CA91CX42_VCSR_CTL_LAS_PCI_MS 0
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#define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0)
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#define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1)
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/* VCSR_BS Register
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* offset FFC
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*/
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#define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27)
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#endif /* _CA91CX42_H */
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