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c1cf725db1
Add the m-phy tuning values for gs101 UFS phy and SoC callbacks gs101_phy_wait_for_calibration() and gs101_phy_wait_for_cdr_lock(). Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240404122559.898930-12-peter.griffin@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
183 lines
6.5 KiB
C
183 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UFS PHY driver data for Google Tensor gs101 SoC
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*
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* Copyright (C) 2024 Linaro Ltd
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* Author: Peter Griffin <peter.griffin@linaro.org>
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*/
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#include "phy-samsung-ufs.h"
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#define TENSOR_GS101_PHY_CTRL 0x3ec8
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#define TENSOR_GS101_PHY_CTRL_MASK 0x1
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#define TENSOR_GS101_PHY_CTRL_EN BIT(0)
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#define PHY_GS101_LANE_OFFSET 0x200
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#define TRSV_REG338 0x338
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#define LN0_MON_RX_CAL_DONE BIT(3)
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#define TRSV_REG339 0x339
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#define LN0_MON_RX_CDR_FLD_CK_MODE_DONE BIT(3)
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#define TRSV_REG222 0x222
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#define LN0_OVRD_RX_CDR_EN BIT(4)
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#define LN0_RX_CDR_EN BIT(3)
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#define PHY_PMA_TRSV_ADDR(reg, lane) (PHY_APB_ADDR((reg) + \
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((lane) * PHY_GS101_LANE_OFFSET)))
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#define PHY_TRSV_REG_CFG_GS101(o, v, d) \
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PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_GS101_LANE_OFFSET)
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/* Calibration for phy initialization */
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static const struct samsung_ufs_phy_cfg tensor_gs101_pre_init_cfg[] = {
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PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x3C, 0x14, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x200, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x201, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x202, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x203, 0x0a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x204, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x205, 0x11, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x207, 0x0c, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2E1, 0xc0, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x22D, 0xb8, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x234, 0x60, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x238, 0x13, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x239, 0x48, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x23A, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x23B, 0x25, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x23C, 0x2a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x23D, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x23E, 0x13, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x23F, 0x13, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x240, 0x4a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x243, 0x40, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x244, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x25D, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x25E, 0x3f, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x25F, 0xff, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x273, 0x33, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x274, 0x50, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x284, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x285, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2A2, 0x04, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x25D, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2FA, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x286, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x287, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x288, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x289, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2B3, 0x04, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2B6, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2B7, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2B8, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2B9, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2BA, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2BB, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2BC, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2BD, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x29E, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2E4, 0x1a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2ED, 0x25, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x269, 0x1a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x2F4, 0x2f, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x34B, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x34C, 0x23, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x34D, 0x23, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x34E, 0x45, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x34F, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x350, 0x31, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x351, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x352, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x353, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x354, 0x01, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
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END_UFS_PHY_CFG,
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};
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static const struct samsung_ufs_phy_cfg tensor_gs101_pre_pwr_hs_config[] = {
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PHY_TRSV_REG_CFG_GS101(0x369, 0x11, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_ANY),
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};
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/* Calibration for HS mode series A/B */
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static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = {
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PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_PWM_ANY),
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PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_PWM_ANY),
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PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_ANY),
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END_UFS_PHY_CFG,
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};
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static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = {
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[CFG_PRE_INIT] = tensor_gs101_pre_init_cfg,
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[CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config,
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[CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config,
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};
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static const char * const tensor_gs101_ufs_phy_clks[] = {
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"ref_clk",
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};
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static int gs101_phy_wait_for_calibration(struct phy *phy, u8 lane)
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{
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struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
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const unsigned int timeout_us = 40000;
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const unsigned int sleep_us = 40;
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u32 val;
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u32 off;
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int err;
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off = PHY_PMA_TRSV_ADDR(TRSV_REG338, lane);
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err = readl_poll_timeout(ufs_phy->reg_pma + off,
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val, (val & LN0_MON_RX_CAL_DONE),
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sleep_us, timeout_us);
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if (err) {
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dev_err(ufs_phy->dev,
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"failed to get phy cal done %d\n", err);
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}
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return err;
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}
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#define DELAY_IN_US 40
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#define RETRY_CNT 100
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static int gs101_phy_wait_for_cdr_lock(struct phy *phy, u8 lane)
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{
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struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
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u32 val;
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int i;
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for (i = 0; i < RETRY_CNT; i++) {
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udelay(DELAY_IN_US);
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val = readl(ufs_phy->reg_pma +
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PHY_PMA_TRSV_ADDR(TRSV_REG339, lane));
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if (val & LN0_MON_RX_CDR_FLD_CK_MODE_DONE)
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return 0;
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udelay(DELAY_IN_US);
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/* Override and enable clock data recovery */
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writel(LN0_OVRD_RX_CDR_EN, ufs_phy->reg_pma +
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PHY_PMA_TRSV_ADDR(TRSV_REG222, lane));
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writel(LN0_OVRD_RX_CDR_EN | LN0_RX_CDR_EN,
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ufs_phy->reg_pma + PHY_PMA_TRSV_ADDR(TRSV_REG222, lane));
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}
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dev_err(ufs_phy->dev, "failed to get cdr lock\n");
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return -ETIMEDOUT;
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}
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const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy = {
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.cfgs = tensor_gs101_ufs_phy_cfgs,
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.isol = {
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.offset = TENSOR_GS101_PHY_CTRL,
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.mask = TENSOR_GS101_PHY_CTRL_MASK,
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.en = TENSOR_GS101_PHY_CTRL_EN,
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},
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.clk_list = tensor_gs101_ufs_phy_clks,
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.num_clks = ARRAY_SIZE(tensor_gs101_ufs_phy_clks),
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.wait_for_cal = gs101_phy_wait_for_calibration,
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.wait_for_cdr = gs101_phy_wait_for_cdr_lock,
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};
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