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c3fcf5d1a4
Add CPU idle support by a call to SoC build-in power management core. Add system reset support by a simple write to system controll register. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
85 lines
3.5 KiB
C
85 lines
3.5 KiB
C
/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Jongse Won <jongse.won@samsung.com>
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*
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* S5PC1XX clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_REGS_PWR
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#define __ASM_ARM_REGS_PWR __FILE__
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#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x))
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/* s5pc100 (0xE0108000) register for power management */
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#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0)
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#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4)
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#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10)
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#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14)
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#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18)
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#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C)
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#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100)
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#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104)
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#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108)
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#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110)
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#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114)
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#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200)
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#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300)
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#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304)
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#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308)
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#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400)
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#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404)
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#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408)
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#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C)
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#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410)
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#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414)
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#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418)
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#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C)
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#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500)
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#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504)
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#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508)
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#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C)
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#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510)
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#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514)
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#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518)
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#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C)
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#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520)
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#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600)
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#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604)
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#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608)
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#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C)
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#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610)
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#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614)
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#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618)
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#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C)
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#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620)
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#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700)
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#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704)
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#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708)
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#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C)
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#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710)
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#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714)
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#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718)
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#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C)
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#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724)
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/* PWR_CFG */
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#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31)
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#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5)
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#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5)
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#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5)
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#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5)
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#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5)
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/* SLEEP_CFG */
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#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0)
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/* OTHERS */
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#define S5PC100_PMU_INT_DISABLE (1 << 24)
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#endif /* __ASM_ARM_REGS_PWR */
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