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5f310b6378
The pageattr-array patch that you currently have in tip/master only
enables it for intel-agp, not the others. The attached enables it for
all drivers currently directly using agp_generic_alloc_page() and
agp_generic_destroy_page() (ocal driver is amd-k7-agp).
The new agp_generic_alloc_pages() interface uses the also new
pageattr array interface API. This makes all AGP drivers that
up to now used generic_{alloc,destroy}_page() use it.
Signed-off-by: Rene Herman <rene.herman@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
462 lines
11 KiB
C
462 lines
11 KiB
C
/*
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* SiS AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <linux/delay.h>
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#include "agp.h"
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#define SIS_ATTBASE 0x90
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#define SIS_APSIZE 0x94
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#define SIS_TLBCNTRL 0x97
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#define SIS_TLBFLUSH 0x98
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#define PCI_DEVICE_ID_SI_662 0x0662
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#define PCI_DEVICE_ID_SI_671 0x0671
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static int __devinitdata agp_sis_force_delay = 0;
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static int __devinitdata agp_sis_agp_spec = -1;
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static int sis_fetch_size(void)
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{
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u8 temp_size;
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int i;
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struct aper_size_info_8 *values;
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pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
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values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if ((temp_size == values[i].size_value) ||
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((temp_size & ~(0x07)) ==
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(values[i].size_value & ~(0x07)))) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static void sis_tlbflush(struct agp_memory *mem)
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{
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pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
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}
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static int sis_configure(void)
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{
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u32 temp;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
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agp_bridge->gatt_bus_addr);
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pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
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current_size->size_value);
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return 0;
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}
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static void sis_cleanup(void)
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{
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struct aper_size_info_8 *previous_size;
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
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(previous_size->size_value & ~(0x03)));
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}
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static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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struct pci_dev *device = NULL;
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u32 command;
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int rate;
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dev_info(&agp_bridge->dev->dev, "AGP %d.%d bridge\n",
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agp_bridge->major_version, agp_bridge->minor_version);
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pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
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command = agp_collect_device_status(bridge, mode, command);
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command |= AGPSTAT_AGP_ENABLE;
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rate = (command & 0x7) << 2;
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for_each_pci_dev(device) {
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u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
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if (!agp)
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continue;
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dev_info(&agp_bridge->dev->dev, "putting AGP V3 device at %s into %dx mode\n",
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pci_name(device), rate);
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pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
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/*
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* Weird: on some sis chipsets any rate change in the target
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* command register triggers a 5ms screwup during which the master
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* cannot be configured
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*/
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if (device->device == bridge->dev->device) {
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dev_info(&agp_bridge->dev->dev, "SiS delay workaround: giving bridge time to recover\n");
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msleep(10);
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}
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}
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}
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static const struct aper_size_info_8 sis_generic_sizes[7] =
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{
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{256, 65536, 6, 99},
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{128, 32768, 5, 83},
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{64, 16384, 4, 67},
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{32, 8192, 3, 51},
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{16, 4096, 2, 35},
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{8, 2048, 1, 19},
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{4, 1024, 0, 3}
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};
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static struct agp_bridge_driver sis_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = sis_generic_sizes,
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.size_type = U8_APER_SIZE,
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.num_aperture_sizes = 7,
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.configure = sis_configure,
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.fetch_size = sis_fetch_size,
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.cleanup = sis_cleanup,
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.tlb_flush = sis_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = NULL,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = agp_generic_insert_memory,
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.remove_memory = agp_generic_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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// chipsets that require the 'delay hack'
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static int sis_broken_chipsets[] __devinitdata = {
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PCI_DEVICE_ID_SI_648,
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PCI_DEVICE_ID_SI_746,
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0 // terminator
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};
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static void __devinit sis_get_driver(struct agp_bridge_data *bridge)
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{
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int i;
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for (i=0; sis_broken_chipsets[i]!=0; ++i)
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if (bridge->dev->device==sis_broken_chipsets[i])
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break;
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if (sis_broken_chipsets[i] || agp_sis_force_delay)
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sis_driver.agp_enable=sis_delayed_enable;
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// sis chipsets that indicate less than agp3.5
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// are not actually fully agp3 compliant
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if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5
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&& agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) {
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sis_driver.aperture_sizes = agp3_generic_sizes;
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sis_driver.size_type = U16_APER_SIZE;
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sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
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sis_driver.configure = agp3_generic_configure;
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sis_driver.fetch_size = agp3_generic_fetch_size;
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sis_driver.cleanup = agp3_generic_cleanup;
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sis_driver.tlb_flush = agp3_generic_tlbflush;
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}
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}
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static int __devinit agp_sis_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_bridge_data *bridge;
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u8 cap_ptr;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return -ENODEV;
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dev_info(&pdev->dev, "SiS chipset [%04x/%04x]\n",
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pdev->vendor, pdev->device);
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->driver = &sis_driver;
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bridge->dev = pdev;
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bridge->capndx = cap_ptr;
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get_agp_version(bridge);
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/* Fill in the mode register */
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pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
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sis_get_driver(bridge);
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pci_set_drvdata(pdev, bridge);
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return agp_add_bridge(bridge);
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}
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static void __devexit agp_sis_remove(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
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agp_remove_bridge(bridge);
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agp_put_bridge(bridge);
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}
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#ifdef CONFIG_PM
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static int agp_sis_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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pci_save_state(pdev);
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pci_set_power_state(pdev, pci_choose_state(pdev, state));
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return 0;
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}
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static int agp_sis_resume(struct pci_dev *pdev)
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{
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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return sis_driver.configure();
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}
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#endif /* CONFIG_PM */
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static struct pci_device_id agp_sis_pci_table[] = {
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_5591,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_530,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_540,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_550,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_620,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_630,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_635,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_645,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_646,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_648,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_650,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_651,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_655,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_661,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_662,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_671,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_730,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_735,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_740,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_741,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_745,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_746,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_SI,
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.device = PCI_DEVICE_ID_SI_760,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
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static struct pci_driver agp_sis_pci_driver = {
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.name = "agpgart-sis",
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.id_table = agp_sis_pci_table,
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.probe = agp_sis_probe,
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.remove = agp_sis_remove,
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#ifdef CONFIG_PM
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.suspend = agp_sis_suspend,
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.resume = agp_sis_resume,
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#endif
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};
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static int __init agp_sis_init(void)
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{
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if (agp_off)
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return -EINVAL;
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return pci_register_driver(&agp_sis_pci_driver);
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}
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static void __exit agp_sis_cleanup(void)
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{
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pci_unregister_driver(&agp_sis_pci_driver);
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}
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module_init(agp_sis_init);
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module_exit(agp_sis_cleanup);
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module_param(agp_sis_force_delay, bool, 0);
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MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
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module_param(agp_sis_agp_spec, int, 0);
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MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
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MODULE_LICENSE("GPL and additional rights");
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