mirror of
https://github.com/torvalds/linux.git
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9471f1f2f5
This modifies our user mode stack expansion code to always take the
mmap_lock for writing before modifying the VM layout.
It's actually something we always technically should have done, but
because we didn't strictly need it, we were being lazy ("opportunistic"
sounds so much better, doesn't it?) about things, and had this hack in
place where we would extend the stack vma in-place without doing the
proper locking.
And it worked fine. We just needed to change vm_start (or, in the case
of grow-up stacks, vm_end) and together with some special ad-hoc locking
using the anon_vma lock and the mm->page_table_lock, it all was fairly
straightforward.
That is, it was all fine until Ruihan Li pointed out that now that the
vma layout uses the maple tree code, we *really* don't just change
vm_start and vm_end any more, and the locking really is broken. Oops.
It's not actually all _that_ horrible to fix this once and for all, and
do proper locking, but it's a bit painful. We have basically three
different cases of stack expansion, and they all work just a bit
differently:
- the common and obvious case is the page fault handling. It's actually
fairly simple and straightforward, except for the fact that we have
something like 24 different versions of it, and you end up in a maze
of twisty little passages, all alike.
- the simplest case is the execve() code that creates a new stack.
There are no real locking concerns because it's all in a private new
VM that hasn't been exposed to anybody, but lockdep still can end up
unhappy if you get it wrong.
- and finally, we have GUP and page pinning, which shouldn't really be
expanding the stack in the first place, but in addition to execve()
we also use it for ptrace(). And debuggers do want to possibly access
memory under the stack pointer and thus need to be able to expand the
stack as a special case.
None of these cases are exactly complicated, but the page fault case in
particular is just repeated slightly differently many many times. And
ia64 in particular has a fairly complicated situation where you can have
both a regular grow-down stack _and_ a special grow-up stack for the
register backing store.
So to make this slightly more manageable, the bulk of this series is to
first create a helper function for the most common page fault case, and
convert all the straightforward architectures to it.
Thus the new 'lock_mm_and_find_vma()' helper function, which ends up
being used by x86, arm, powerpc, mips, riscv, alpha, arc, csky, hexagon,
loongarch, nios2, sh, sparc32, and xtensa. So we not only convert more
than half the architectures, we now have more shared code and avoid some
of those twisty little passages.
And largely due to this common helper function, the full diffstat of
this series ends up deleting more lines than it adds.
That still leaves eight architectures (ia64, m68k, microblaze, openrisc,
parisc, s390, sparc64 and um) that end up doing 'expand_stack()'
manually because they are doing something slightly different from the
normal pattern. Along with the couple of special cases in execve() and
GUP.
So there's a couple of patches that first create 'locked' helper
versions of the stack expansion functions, so that there's a obvious
path forward in the conversion. The execve() case is then actually
pretty simple, and is a nice cleanup from our old "grow-up stackls are
special, because at execve time even they grow down".
The #ifdef CONFIG_STACK_GROWSUP in that code just goes away, because
it's just more straightforward to write out the stack expansion there
manually, instead od having get_user_pages_remote() do it for us in some
situations but not others and have to worry about locking rules for GUP.
And the final step is then to just convert the remaining odd cases to a
new world order where 'expand_stack()' is called with the mmap_lock held
for reading, but where it might drop it and upgrade it to a write, only
to return with it held for reading (in the success case) or with it
completely dropped (in the failure case).
In the process, we remove all the stack expansion from GUP (where
dropping the lock wouldn't be ok without special rules anyway), and add
it in manually to __access_remote_vm() for ptrace().
Thanks to Adrian Glaubitz and Frank Scheiner who tested the ia64 cases.
Everything else here felt pretty straightforward, but the ia64 rules for
stack expansion are really quite odd and very different from everything
else. Also thanks to Vegard Nossum who caught me getting one of those
odd conditions entirely the wrong way around.
Anyway, I think I want to actually move all the stack expansion code to
a whole new file of its own, rather than have it split up between
mm/mmap.c and mm/memory.c, but since this will have to be backported to
the initial maple tree vma introduction anyway, I tried to keep the
patches _fairly_ minimal.
Also, while I don't think it's valid to expand the stack from GUP, the
final patch in here is a "warn if some crazy GUP user wants to try to
expand the stack" patch. That one will be reverted before the final
release, but it's left to catch any odd cases during the merge window
and release candidates.
Reported-by: Ruihan Li <lrh2000@pku.edu.cn>
* branch 'expand-stack':
gup: add warning if some caller would seem to want stack expansion
mm: always expand the stack with the mmap write lock held
execve: expand new process stack manually ahead of time
mm: make find_extend_vma() fail if write lock not held
powerpc/mm: convert coprocessor fault to lock_mm_and_find_vma()
mm/fault: convert remaining simple cases to lock_mm_and_find_vma()
arm/mm: Convert to using lock_mm_and_find_vma()
riscv/mm: Convert to using lock_mm_and_find_vma()
mips/mm: Convert to using lock_mm_and_find_vma()
powerpc/mm: Convert to using lock_mm_and_find_vma()
arm64/mm: Convert to using lock_mm_and_find_vma()
mm: make the page fault mmap locking killable
mm: introduce new 'lock_mm_and_find_vma()' page fault helper
810 lines
24 KiB
Plaintext
810 lines
24 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config XTENSA
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def_bool y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_BINFMT_FLAT if !MMU
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select ARCH_HAS_CURRENT_STACK_POINTER
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select ARCH_HAS_DMA_PREP_COHERENT if MMU
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_KCOV
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select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
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select ARCH_HAS_DMA_SET_UNCACHED if MMU
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select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
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select ARCH_HAS_STRNLEN_USER
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select ARCH_USE_MEMTEST
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_WANT_IPC_PARSE_VERSION
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select BUILDTIME_TABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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select DMA_NONCOHERENT_MMAP if MMU
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select GENERIC_ATOMIC64
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select GENERIC_IRQ_SHOW
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select GENERIC_LIB_CMPDI2
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select GENERIC_LIB_MULDI3
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select GENERIC_LIB_UCMPDI2
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select GENERIC_PCI_IOMAP
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select GENERIC_SCHED_CLOCK
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
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select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
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select HAVE_ARCH_KCSAN
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_ASM_MODVERSIONS
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select HAVE_CONTEXT_TRACKING_USER
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_CONTIGUOUS
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select HAVE_EXIT_THREAD
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select HAVE_FUNCTION_TRACER
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select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000
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select HAVE_HW_BREAKPOINT if PERF_EVENTS
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select HAVE_IRQ_TIME_ACCOUNTING
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select HAVE_PCI
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select HAVE_PERF_EVENTS
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select HAVE_STACKPROTECTOR
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select HAVE_SYSCALL_TRACEPOINTS
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select IRQ_DOMAIN
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select LOCK_MM_AND_FIND_VMA
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select MODULES_USE_ELF_RELA
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select PERF_USE_VMALLOC
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select TRACE_IRQFLAGS_SUPPORT
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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primarily for embedded systems. These processors are both
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configurable and extensible. The Linux port to the Xtensa
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architecture supports all processor configurations and extensions,
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with reasonable minimum requirements. The Xtensa Linux project has
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a home page at <http://www.linux-xtensa.org/>.
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config GENERIC_HWEIGHT
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def_bool y
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config ARCH_HAS_ILOG2_U32
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def_bool n
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config ARCH_HAS_ILOG2_U64
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def_bool n
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config NO_IOPORT_MAP
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def_bool n
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config HZ
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int
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default 100
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config LOCKDEP_SUPPORT
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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config MMU
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def_bool n
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select PFAULT
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config HAVE_XTENSA_GPIO32
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def_bool n
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config KASAN_SHADOW_OFFSET
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hex
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default 0x6e400000
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config CPU_BIG_ENDIAN
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def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
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config CPU_LITTLE_ENDIAN
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def_bool !CPU_BIG_ENDIAN
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config CC_HAVE_CALL0_ABI
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def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1)
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menu "Processor type and features"
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choice
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prompt "Xtensa Processor Configuration"
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default XTENSA_VARIANT_FSF
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config XTENSA_VARIANT_FSF
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bool "fsf - default (not generic) configuration"
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select MMU
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config XTENSA_VARIANT_DC232B
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bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
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select MMU
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select HAVE_XTENSA_GPIO32
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help
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This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
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config XTENSA_VARIANT_DC233C
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bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
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select MMU
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select HAVE_XTENSA_GPIO32
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help
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This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
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config XTENSA_VARIANT_CUSTOM
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bool "Custom Xtensa processor configuration"
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select HAVE_XTENSA_GPIO32
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help
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Select this variant to use a custom Xtensa processor configuration.
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You will be prompted for a processor variant CORENAME.
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endchoice
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config XTENSA_VARIANT_CUSTOM_NAME
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string "Xtensa Processor Custom Core Variant Name"
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depends on XTENSA_VARIANT_CUSTOM
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help
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Provide the name of a custom Xtensa processor variant.
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This CORENAME selects arch/xtensa/variant/CORENAME.
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Don't forget you have to select MMU if you have one.
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config XTENSA_VARIANT_NAME
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string
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default "dc232b" if XTENSA_VARIANT_DC232B
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default "dc233c" if XTENSA_VARIANT_DC233C
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default "fsf" if XTENSA_VARIANT_FSF
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default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
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config XTENSA_VARIANT_MMU
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bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
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depends on XTENSA_VARIANT_CUSTOM
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default y
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select MMU
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help
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Build a Conventional Kernel with full MMU support,
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ie: it supports a TLB with auto-loading, page protection.
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config XTENSA_VARIANT_HAVE_PERF_EVENTS
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bool "Core variant has Performance Monitor Module"
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depends on XTENSA_VARIANT_CUSTOM
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default n
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help
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Enable if core variant has Performance Monitor Module with
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External Registers Interface.
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If unsure, say N.
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config XTENSA_FAKE_NMI
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bool "Treat PMM IRQ as NMI"
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depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
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default n
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help
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If PMM IRQ is the only IRQ at EXCM level it is safe to
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treat it as NMI, which improves accuracy of profiling.
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If there are other interrupts at or above PMM IRQ priority level
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but not above the EXCM level, PMM IRQ still may be treated as NMI,
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but only if these IRQs are not used. There will be a build warning
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saying that this is not safe, and a bugcheck if one of these IRQs
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actually fire.
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If unsure, say N.
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config PFAULT
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bool "Handle protection faults" if EXPERT && !MMU
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default y
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help
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Handle protection faults. MMU configurations must enable it.
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noMMU configurations may disable it if used memory map never
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generates protection faults or faults are always fatal.
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If unsure, say Y.
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config XTENSA_UNALIGNED_USER
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bool "Unaligned memory access in user space"
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help
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The Xtensa architecture currently does not handle unaligned
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memory accesses in hardware but through an exception handler.
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Per default, unaligned memory accesses are disabled in user space.
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Say Y here to enable unaligned memory access in user space.
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config XTENSA_LOAD_STORE
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bool "Load/store exception handler for memory only readable with l32"
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help
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The Xtensa architecture only allows reading memory attached to its
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instruction bus with l32r and l32i instructions, all other
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instructions raise an exception with the LoadStoreErrorCause code.
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This makes it hard to use some configurations, e.g. store string
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literals in FLASH memory attached to the instruction bus.
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Say Y here to enable exception handler that allows transparent
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byte and 2-byte access to memory attached to instruction bus.
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config HAVE_SMP
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bool "System Supports SMP (MX)"
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depends on XTENSA_VARIANT_CUSTOM
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select XTENSA_MX
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help
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This option is used to indicate that the system-on-a-chip (SOC)
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supports Multiprocessing. Multiprocessor support implemented above
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the CPU core definition and currently needs to be selected manually.
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Multiprocessor support is implemented with external cache and
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interrupt controllers.
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The MX interrupt distributer adds Interprocessor Interrupts
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and causes the IRQ numbers to be increased by 4 for devices
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like the open cores ethernet driver and the serial interface.
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You still have to select "Enable SMP" to enable SMP on this SOC.
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config SMP
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bool "Enable Symmetric multi-processing support"
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depends on HAVE_SMP
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select GENERIC_SMP_IDLE_THREAD
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help
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Enabled SMP Software; allows more than one CPU/CORE
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to be activated during startup.
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config NR_CPUS
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depends on SMP
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int "Maximum number of CPUs (2-32)"
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range 2 32
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default "4"
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config HOTPLUG_CPU
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bool "Enable CPU hotplug support"
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depends on SMP
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help
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Say Y here to allow turning CPUs off and on. CPUs can be
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controlled through /sys/devices/system/cpu.
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Say N if you want to disable CPU hotplug.
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config SECONDARY_RESET_VECTOR
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bool "Secondary cores use alternative reset vector"
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default y
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depends on HAVE_SMP
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help
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Secondary cores may be configured to use alternative reset vector,
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or all cores may use primary reset vector.
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Say Y here to supply handler for the alternative reset location.
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config FAST_SYSCALL_XTENSA
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bool "Enable fast atomic syscalls"
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default n
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help
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fast_syscall_xtensa is a syscall that can make atomic operations
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on UP kernel when processor has no s32c1i support.
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This syscall is deprecated. It may have issues when called with
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invalid arguments. It is provided only for backwards compatibility.
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Only enable it if your userspace software requires it.
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If unsure, say N.
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config FAST_SYSCALL_SPILL_REGISTERS
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bool "Enable spill registers syscall"
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default n
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help
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fast_syscall_spill_registers is a syscall that spills all active
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register windows of a calling userspace task onto its stack.
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This syscall is deprecated. It may have issues when called with
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invalid arguments. It is provided only for backwards compatibility.
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Only enable it if your userspace software requires it.
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If unsure, say N.
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choice
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prompt "Kernel ABI"
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default KERNEL_ABI_DEFAULT
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help
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Select ABI for the kernel code. This ABI is independent of the
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supported userspace ABI and any combination of the
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kernel/userspace ABI is possible and should work.
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In case both kernel and userspace support only call0 ABI
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all register windows support code will be omitted from the
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build.
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If unsure, choose the default ABI.
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config KERNEL_ABI_DEFAULT
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bool "Default ABI"
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help
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Select this option to compile kernel code with the default ABI
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selected for the toolchain.
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Normally cores with windowed registers option use windowed ABI and
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cores without it use call0 ABI.
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config KERNEL_ABI_CALL0
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bool "Call0 ABI" if CC_HAVE_CALL0_ABI
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help
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Select this option to compile kernel code with call0 ABI even with
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toolchain that defaults to windowed ABI.
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When this option is not selected the default toolchain ABI will
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be used for the kernel code.
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endchoice
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config USER_ABI_CALL0
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bool
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choice
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prompt "Userspace ABI"
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default USER_ABI_DEFAULT
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help
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Select supported userspace ABI.
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If unsure, choose the default ABI.
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config USER_ABI_DEFAULT
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bool "Default ABI only"
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help
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Assume default userspace ABI. For XEA2 cores it is windowed ABI.
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call0 ABI binaries may be run on such kernel, but signal delivery
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will not work correctly for them.
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config USER_ABI_CALL0_ONLY
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bool "Call0 ABI only"
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select USER_ABI_CALL0
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help
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Select this option to support only call0 ABI in userspace.
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Windowed ABI binaries will crash with a segfault caused by
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an illegal instruction exception on the first 'entry' opcode.
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Choose this option if you're planning to run only user code
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built with call0 ABI.
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config USER_ABI_CALL0_PROBE
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bool "Support both windowed and call0 ABI by probing"
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select USER_ABI_CALL0
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help
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Select this option to support both windowed and call0 userspace
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ABIs. When enabled all processes are started with PS.WOE disabled
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and a fast user exception handler for an illegal instruction is
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used to turn on PS.WOE bit on the first 'entry' opcode executed by
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the userspace.
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This option should be enabled for the kernel that must support
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both call0 and windowed ABIs in userspace at the same time.
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Note that Xtensa ISA does not guarantee that entry opcode will
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raise an illegal instruction exception on cores with XEA2 when
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PS.WOE is disabled, check whether the target core supports it.
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endchoice
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endmenu
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config XTENSA_CALIBRATE_CCOUNT
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def_bool n
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help
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On some platforms (XT2000, for example), the CPU clock rate can
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vary. The frequency can be determined, however, by measuring
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against a well known, fixed frequency, such as an UART oscillator.
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config SERIAL_CONSOLE
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def_bool n
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config PLATFORM_HAVE_XIP
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def_bool n
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menu "Platform options"
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choice
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prompt "Xtensa System Type"
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default XTENSA_PLATFORM_ISS
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config XTENSA_PLATFORM_ISS
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bool "ISS"
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select XTENSA_CALIBRATE_CCOUNT
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select SERIAL_CONSOLE
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help
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ISS is an acronym for Tensilica's Instruction Set Simulator.
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config XTENSA_PLATFORM_XT2000
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bool "XT2000"
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help
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XT2000 is the name of Tensilica's feature-rich emulation platform.
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This hardware is capable of running a full Linux distribution.
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config XTENSA_PLATFORM_XTFPGA
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bool "XTFPGA"
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select ETHOC if ETHERNET
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select PLATFORM_WANT_DEFAULT_MEM if !MMU
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select SERIAL_CONSOLE
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select XTENSA_CALIBRATE_CCOUNT
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select PLATFORM_HAVE_XIP
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help
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XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
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This hardware is capable of running a full Linux distribution.
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|
|
|
endchoice
|
|
|
|
config PLATFORM_NR_IRQS
|
|
int
|
|
default 3 if XTENSA_PLATFORM_XT2000
|
|
default 0
|
|
|
|
config XTENSA_CPU_CLOCK
|
|
int "CPU clock rate [MHz]"
|
|
depends on !XTENSA_CALIBRATE_CCOUNT
|
|
default 16
|
|
|
|
config GENERIC_CALIBRATE_DELAY
|
|
bool "Auto calibration of the BogoMIPS value"
|
|
help
|
|
The BogoMIPS value can easily be derived from the CPU frequency.
|
|
|
|
config CMDLINE_BOOL
|
|
bool "Default bootloader kernel arguments"
|
|
|
|
config CMDLINE
|
|
string "Initial kernel command string"
|
|
depends on CMDLINE_BOOL
|
|
default "console=ttyS0,38400 root=/dev/ram"
|
|
help
|
|
On some architectures (EBSA110 and CATS), there is currently no way
|
|
for the boot loader to pass arguments to the kernel. For these
|
|
architectures, you should supply some command-line options at build
|
|
time by entering them here. As a minimum, you should specify the
|
|
memory size and the root device (e.g., mem=64M root=/dev/nfs).
|
|
|
|
config USE_OF
|
|
bool "Flattened Device Tree support"
|
|
select OF
|
|
select OF_EARLY_FLATTREE
|
|
help
|
|
Include support for flattened device tree machine descriptions.
|
|
|
|
config BUILTIN_DTB_SOURCE
|
|
string "DTB to build into the kernel image"
|
|
depends on OF
|
|
|
|
config PARSE_BOOTPARAM
|
|
bool "Parse bootparam block"
|
|
default y
|
|
help
|
|
Parse parameters passed to the kernel from the bootloader. It may
|
|
be disabled if the kernel is known to run without the bootloader.
|
|
|
|
If unsure, say Y.
|
|
|
|
choice
|
|
prompt "Semihosting interface"
|
|
default XTENSA_SIMCALL_ISS
|
|
depends on XTENSA_PLATFORM_ISS
|
|
help
|
|
Choose semihosting interface that will be used for serial port,
|
|
block device and networking.
|
|
|
|
config XTENSA_SIMCALL_ISS
|
|
bool "simcall"
|
|
help
|
|
Use simcall instruction. simcall is only available on simulators,
|
|
it does nothing on hardware.
|
|
|
|
config XTENSA_SIMCALL_GDBIO
|
|
bool "GDBIO"
|
|
help
|
|
Use break instruction. It is available on real hardware when GDB
|
|
is attached to it via JTAG.
|
|
|
|
endchoice
|
|
|
|
config BLK_DEV_SIMDISK
|
|
tristate "Host file-based simulated block device support"
|
|
default n
|
|
depends on XTENSA_PLATFORM_ISS && BLOCK
|
|
help
|
|
Create block devices that map to files in the host file system.
|
|
Device binding to host file may be changed at runtime via proc
|
|
interface provided the device is not in use.
|
|
|
|
config BLK_DEV_SIMDISK_COUNT
|
|
int "Number of host file-based simulated block devices"
|
|
range 1 10
|
|
depends on BLK_DEV_SIMDISK
|
|
default 2
|
|
help
|
|
This is the default minimal number of created block devices.
|
|
Kernel/module parameter 'simdisk_count' may be used to change this
|
|
value at runtime. More file names (but no more than 10) may be
|
|
specified as parameters, simdisk_count grows accordingly.
|
|
|
|
config SIMDISK0_FILENAME
|
|
string "Host filename for the first simulated device"
|
|
depends on BLK_DEV_SIMDISK = y
|
|
default ""
|
|
help
|
|
Attach a first simdisk to a host file. Conventionally, this file
|
|
contains a root file system.
|
|
|
|
config SIMDISK1_FILENAME
|
|
string "Host filename for the second simulated device"
|
|
depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
|
|
default ""
|
|
help
|
|
Another simulated disk in a host file for a buildroot-independent
|
|
storage.
|
|
|
|
config XTFPGA_LCD
|
|
bool "Enable XTFPGA LCD driver"
|
|
depends on XTENSA_PLATFORM_XTFPGA
|
|
default n
|
|
help
|
|
There's a 2x16 LCD on most of XTFPGA boards, kernel may output
|
|
progress messages there during bootup/shutdown. It may be useful
|
|
during board bringup.
|
|
|
|
If unsure, say N.
|
|
|
|
config XTFPGA_LCD_BASE_ADDR
|
|
hex "XTFPGA LCD base address"
|
|
depends on XTFPGA_LCD
|
|
default "0x0d0c0000"
|
|
help
|
|
Base address of the LCD controller inside KIO region.
|
|
Different boards from XTFPGA family have LCD controller at different
|
|
addresses. Please consult prototyping user guide for your board for
|
|
the correct address. Wrong address here may lead to hardware lockup.
|
|
|
|
config XTFPGA_LCD_8BIT_ACCESS
|
|
bool "Use 8-bit access to XTFPGA LCD"
|
|
depends on XTFPGA_LCD
|
|
default n
|
|
help
|
|
LCD may be connected with 4- or 8-bit interface, 8-bit access may
|
|
only be used with 8-bit interface. Please consult prototyping user
|
|
guide for your board for the correct interface width.
|
|
|
|
comment "Kernel memory layout"
|
|
|
|
config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
bool "Initialize Xtensa MMU inside the Linux kernel code"
|
|
depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
|
|
default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
|
|
help
|
|
Earlier version initialized the MMU in the exception vector
|
|
before jumping to _startup in head.S and had an advantage that
|
|
it was possible to place a software breakpoint at 'reset' and
|
|
then enter your normal kernel breakpoints once the MMU was mapped
|
|
to the kernel mappings (0XC0000000).
|
|
|
|
This unfortunately won't work for U-Boot and likely also won't
|
|
work for using KEXEC to have a hot kernel ready for doing a
|
|
KDUMP.
|
|
|
|
So now the MMU is initialized in head.S but it's necessary to
|
|
use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
|
|
xt-gdb can't place a Software Breakpoint in the 0XD region prior
|
|
to mapping the MMU and after mapping even if the area of low memory
|
|
was mapped gdb wouldn't remove the breakpoint on hitting it as the
|
|
PC wouldn't match. Since Hardware Breakpoints are recommended for
|
|
Linux configurations it seems reasonable to just assume they exist
|
|
and leave this older mechanism for unfortunate souls that choose
|
|
not to follow Tensilica's recommendation.
|
|
|
|
Selecting this will cause U-Boot to set the KERNEL Load and Entry
|
|
address at 0x00003000 instead of the mapped std of 0xD0003000.
|
|
|
|
If in doubt, say Y.
|
|
|
|
config XIP_KERNEL
|
|
bool "Kernel Execute-In-Place from ROM"
|
|
depends on PLATFORM_HAVE_XIP
|
|
help
|
|
Execute-In-Place allows the kernel to run from non-volatile storage
|
|
directly addressable by the CPU, such as NOR flash. This saves RAM
|
|
space since the text section of the kernel is not loaded from flash
|
|
to RAM. Read-write sections, such as the data section and stack,
|
|
are still copied to RAM. The XIP kernel is not compressed since
|
|
it has to run directly from flash, so it will take more space to
|
|
store it. The flash address used to link the kernel object files,
|
|
and for storing it, is configuration dependent. Therefore, if you
|
|
say Y here, you must know the proper physical address where to
|
|
store the kernel image depending on your own flash memory usage.
|
|
|
|
Also note that the make target becomes "make xipImage" rather than
|
|
"make Image" or "make uImage". The final kernel binary to put in
|
|
ROM memory will be arch/xtensa/boot/xipImage.
|
|
|
|
If unsure, say N.
|
|
|
|
config MEMMAP_CACHEATTR
|
|
hex "Cache attributes for the memory address space"
|
|
depends on !MMU
|
|
default 0x22222222
|
|
help
|
|
These cache attributes are set up for noMMU systems. Each hex digit
|
|
specifies cache attributes for the corresponding 512MB memory
|
|
region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
|
|
bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
|
|
|
|
Cache attribute values are specific for the MMU type.
|
|
For region protection MMUs:
|
|
1: WT cached,
|
|
2: cache bypass,
|
|
4: WB cached,
|
|
f: illegal.
|
|
For full MMU:
|
|
bit 0: executable,
|
|
bit 1: writable,
|
|
bits 2..3:
|
|
0: cache bypass,
|
|
1: WB cache,
|
|
2: WT cache,
|
|
3: special (c and e are illegal, f is reserved).
|
|
For MPU:
|
|
0: illegal,
|
|
1: WB cache,
|
|
2: WB, no-write-allocate cache,
|
|
3: WT cache,
|
|
4: cache bypass.
|
|
|
|
config KSEG_PADDR
|
|
hex "Physical address of the KSEG mapping"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
|
|
default 0x00000000
|
|
help
|
|
This is the physical address where KSEG is mapped. Please refer to
|
|
the chosen KSEG layout help for the required address alignment.
|
|
Unpacked kernel image (including vectors) must be located completely
|
|
within KSEG.
|
|
Physical memory below this address is not available to linux.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
config KERNEL_VIRTUAL_ADDRESS
|
|
hex "Kernel virtual address"
|
|
depends on MMU && XIP_KERNEL
|
|
default 0xd0003000
|
|
help
|
|
This is the virtual address where the XIP kernel is mapped.
|
|
XIP kernel may be mapped into KSEG or KIO region, virtual address
|
|
provided here must match kernel load address provided in
|
|
KERNEL_LOAD_ADDRESS.
|
|
|
|
config KERNEL_LOAD_ADDRESS
|
|
hex "Kernel load address"
|
|
default 0x60003000 if !MMU
|
|
default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
This is the address where the kernel is loaded.
|
|
It is virtual address for MMUv2 configurations and physical address
|
|
for all other configurations.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
choice
|
|
prompt "Relocatable vectors location"
|
|
default XTENSA_VECTORS_IN_TEXT
|
|
help
|
|
Choose whether relocatable vectors are merged into the kernel .text
|
|
or placed separately at runtime. This option does not affect
|
|
configurations without VECBASE register where vectors are always
|
|
placed at their hardware-defined locations.
|
|
|
|
config XTENSA_VECTORS_IN_TEXT
|
|
bool "Merge relocatable vectors into kernel text"
|
|
depends on !MTD_XIP
|
|
help
|
|
This option puts relocatable vectors into the kernel .text section
|
|
with proper alignment.
|
|
This is a safe choice for most configurations.
|
|
|
|
config XTENSA_VECTORS_SEPARATE
|
|
bool "Put relocatable vectors at fixed address"
|
|
help
|
|
This option puts relocatable vectors at specific virtual address.
|
|
Vectors are merged with the .init data in the kernel image and
|
|
are copied into their designated location during kernel startup.
|
|
Use it to put vectors into IRAM or out of FLASH on kernels with
|
|
XIP-aware MTD support.
|
|
|
|
endchoice
|
|
|
|
config VECTORS_ADDR
|
|
hex "Kernel vectors virtual address"
|
|
default 0x00000000
|
|
depends on XTENSA_VECTORS_SEPARATE
|
|
help
|
|
This is the virtual address of the (relocatable) vectors base.
|
|
It must be within KSEG if MMU is used.
|
|
|
|
config XIP_DATA_ADDR
|
|
hex "XIP kernel data virtual address"
|
|
depends on XIP_KERNEL
|
|
default 0x00000000
|
|
help
|
|
This is the virtual address where XIP kernel data is copied.
|
|
It must be within KSEG if MMU is used.
|
|
|
|
config PLATFORM_WANT_DEFAULT_MEM
|
|
def_bool n
|
|
|
|
config DEFAULT_MEM_START
|
|
hex
|
|
prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
|
|
default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
|
|
default 0x00000000
|
|
help
|
|
This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
|
|
in noMMU configurations.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
choice
|
|
prompt "KSEG layout"
|
|
depends on MMU
|
|
default XTENSA_KSEG_MMU_V2
|
|
|
|
config XTENSA_KSEG_MMU_V2
|
|
bool "MMUv2: 128MB cached + 128MB uncached"
|
|
help
|
|
MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
|
|
at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
|
|
without cache.
|
|
KSEG_PADDR must be aligned to 128MB.
|
|
|
|
config XTENSA_KSEG_256M
|
|
bool "256MB cached + 256MB uncached"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
|
|
with cache and to 0xc0000000 without cache.
|
|
KSEG_PADDR must be aligned to 256MB.
|
|
|
|
config XTENSA_KSEG_512M
|
|
bool "512MB cached + 512MB uncached"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
|
|
with cache and to 0xc0000000 without cache.
|
|
KSEG_PADDR must be aligned to 256MB.
|
|
|
|
endchoice
|
|
|
|
config HIGHMEM
|
|
bool "High Memory Support"
|
|
depends on MMU
|
|
select KMAP_LOCAL
|
|
help
|
|
Linux can use the full amount of RAM in the system by
|
|
default. However, the default MMUv2 setup only maps the
|
|
lowermost 128 MB of memory linearly to the areas starting
|
|
at 0xd0000000 (cached) and 0xd8000000 (uncached).
|
|
When there are more than 128 MB memory in the system not
|
|
all of it can be "permanently mapped" by the kernel.
|
|
The physical memory that's not permanently mapped is called
|
|
"high memory".
|
|
|
|
If you are compiling a kernel which will never run on a
|
|
machine with more than 128 MB total physical RAM, answer
|
|
N here.
|
|
|
|
If unsure, say Y.
|
|
|
|
config ARCH_FORCE_MAX_ORDER
|
|
int "Order of maximal physically contiguous allocations"
|
|
default "10"
|
|
help
|
|
The kernel page allocator limits the size of maximal physically
|
|
contiguous allocations. The limit is called MAX_ORDER and it
|
|
defines the maximal power of two of number of pages that can be
|
|
allocated as a single contiguous block. This option allows
|
|
overriding the default setting when ability to allocate very
|
|
large blocks of physically contiguous memory is required.
|
|
|
|
Don't change if unsure.
|
|
|
|
endmenu
|
|
|
|
menu "Power management options"
|
|
|
|
config ARCH_HIBERNATION_POSSIBLE
|
|
def_bool y
|
|
|
|
source "kernel/power/Kconfig"
|
|
|
|
endmenu
|