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3593cd5396
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
289 lines
7.3 KiB
C
289 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ADXL345 3-Axis Digital Accelerometer IIO core driver
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*
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* Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com>
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*
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* Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
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*/
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include "adxl345.h"
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#define ADXL345_REG_DEVID 0x00
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#define ADXL345_REG_OFSX 0x1e
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#define ADXL345_REG_OFSY 0x1f
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#define ADXL345_REG_OFSZ 0x20
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#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
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#define ADXL345_REG_BW_RATE 0x2C
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#define ADXL345_REG_POWER_CTL 0x2D
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#define ADXL345_REG_DATA_FORMAT 0x31
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#define ADXL345_REG_DATAX0 0x32
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#define ADXL345_REG_DATAY0 0x34
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#define ADXL345_REG_DATAZ0 0x36
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#define ADXL345_REG_DATA_AXIS(index) \
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(ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
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#define ADXL345_BW_RATE GENMASK(3, 0)
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#define ADXL345_BASE_RATE_NANO_HZ 97656250LL
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#define NHZ_PER_HZ 1000000000LL
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#define ADXL345_POWER_CTL_MEASURE BIT(3)
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#define ADXL345_POWER_CTL_STANDBY 0x00
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#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */
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#define ADXL345_DATA_FORMAT_2G 0
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#define ADXL345_DATA_FORMAT_4G 1
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#define ADXL345_DATA_FORMAT_8G 2
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#define ADXL345_DATA_FORMAT_16G 3
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#define ADXL345_DEVID 0xE5
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/*
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* In full-resolution mode, scale factor is maintained at ~4 mg/LSB
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* in all g ranges.
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*
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* At +/- 16g with 13-bit resolution, scale is computed as:
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* (16 + 16) * 9.81 / (2^13 - 1) = 0.0383
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*/
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static const int adxl345_uscale = 38300;
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/*
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* The Datasheet lists a resolution of Resolution is ~49 mg per LSB. That's
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* ~480mm/s**2 per LSB.
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*/
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static const int adxl375_uscale = 480000;
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struct adxl345_data {
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struct regmap *regmap;
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u8 data_range;
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enum adxl345_device_type type;
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};
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#define ADXL345_CHANNEL(index, axis) { \
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.type = IIO_ACCEL, \
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.modified = 1, \
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.channel2 = IIO_MOD_##axis, \
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.address = index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_CALIBBIAS), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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}
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static const struct iio_chan_spec adxl345_channels[] = {
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ADXL345_CHANNEL(0, X),
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ADXL345_CHANNEL(1, Y),
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ADXL345_CHANNEL(2, Z),
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};
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static int adxl345_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct adxl345_data *data = iio_priv(indio_dev);
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__le16 accel;
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long long samp_freq_nhz;
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unsigned int regval;
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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/*
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* Data is stored in adjacent registers:
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* ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
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* and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
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*/
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ret = regmap_bulk_read(data->regmap,
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ADXL345_REG_DATA_AXIS(chan->address),
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&accel, sizeof(accel));
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if (ret < 0)
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return ret;
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*val = sign_extend32(le16_to_cpu(accel), 12);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = 0;
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switch (data->type) {
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case ADXL345:
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*val2 = adxl345_uscale;
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break;
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case ADXL375:
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*val2 = adxl375_uscale;
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break;
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}
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return IIO_VAL_INT_PLUS_MICRO;
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case IIO_CHAN_INFO_CALIBBIAS:
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ret = regmap_read(data->regmap,
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ADXL345_REG_OFS_AXIS(chan->address), ®val);
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if (ret < 0)
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return ret;
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/*
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* 8-bit resolution at +/- 2g, that is 4x accel data scale
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* factor
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*/
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*val = sign_extend32(regval, 7) * 4;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SAMP_FREQ:
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ret = regmap_read(data->regmap, ADXL345_REG_BW_RATE, ®val);
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if (ret < 0)
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return ret;
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samp_freq_nhz = ADXL345_BASE_RATE_NANO_HZ <<
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(regval & ADXL345_BW_RATE);
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*val = div_s64_rem(samp_freq_nhz, NHZ_PER_HZ, val2);
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return IIO_VAL_INT_PLUS_NANO;
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}
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return -EINVAL;
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}
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static int adxl345_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct adxl345_data *data = iio_priv(indio_dev);
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s64 n;
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switch (mask) {
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case IIO_CHAN_INFO_CALIBBIAS:
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/*
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* 8-bit resolution at +/- 2g, that is 4x accel data scale
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* factor
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*/
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return regmap_write(data->regmap,
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ADXL345_REG_OFS_AXIS(chan->address),
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val / 4);
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case IIO_CHAN_INFO_SAMP_FREQ:
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n = div_s64(val * NHZ_PER_HZ + val2, ADXL345_BASE_RATE_NANO_HZ);
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return regmap_update_bits(data->regmap, ADXL345_REG_BW_RATE,
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ADXL345_BW_RATE,
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clamp_val(ilog2(n), 0,
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ADXL345_BW_RATE));
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}
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return -EINVAL;
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}
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static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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long mask)
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{
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switch (mask) {
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case IIO_CHAN_INFO_CALIBBIAS:
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SAMP_FREQ:
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return IIO_VAL_INT_PLUS_NANO;
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default:
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return -EINVAL;
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}
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}
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static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
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"0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200"
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);
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static struct attribute *adxl345_attrs[] = {
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&iio_const_attr_sampling_frequency_available.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group adxl345_attrs_group = {
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.attrs = adxl345_attrs,
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};
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static const struct iio_info adxl345_info = {
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.attrs = &adxl345_attrs_group,
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.read_raw = adxl345_read_raw,
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.write_raw = adxl345_write_raw,
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.write_raw_get_fmt = adxl345_write_raw_get_fmt,
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};
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int adxl345_core_probe(struct device *dev, struct regmap *regmap,
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enum adxl345_device_type type, const char *name)
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{
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struct adxl345_data *data;
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struct iio_dev *indio_dev;
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u32 regval;
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int ret;
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ret = regmap_read(regmap, ADXL345_REG_DEVID, ®val);
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if (ret < 0) {
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dev_err(dev, "Error reading device ID: %d\n", ret);
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return ret;
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}
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if (regval != ADXL345_DEVID) {
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dev_err(dev, "Invalid device ID: %x, expected %x\n",
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regval, ADXL345_DEVID);
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return -ENODEV;
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}
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indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
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if (!indio_dev)
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return -ENOMEM;
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data = iio_priv(indio_dev);
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dev_set_drvdata(dev, indio_dev);
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data->regmap = regmap;
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data->type = type;
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/* Enable full-resolution mode */
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data->data_range = ADXL345_DATA_FORMAT_FULL_RES;
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ret = regmap_write(data->regmap, ADXL345_REG_DATA_FORMAT,
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data->data_range);
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if (ret < 0) {
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dev_err(dev, "Failed to set data range: %d\n", ret);
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return ret;
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}
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indio_dev->name = name;
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indio_dev->info = &adxl345_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = adxl345_channels;
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indio_dev->num_channels = ARRAY_SIZE(adxl345_channels);
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/* Enable measurement mode */
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ret = regmap_write(data->regmap, ADXL345_REG_POWER_CTL,
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ADXL345_POWER_CTL_MEASURE);
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if (ret < 0) {
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dev_err(dev, "Failed to enable measurement mode: %d\n", ret);
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return ret;
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}
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ret = iio_device_register(indio_dev);
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if (ret < 0) {
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dev_err(dev, "iio_device_register failed: %d\n", ret);
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regmap_write(data->regmap, ADXL345_REG_POWER_CTL,
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ADXL345_POWER_CTL_STANDBY);
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(adxl345_core_probe);
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int adxl345_core_remove(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct adxl345_data *data = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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return regmap_write(data->regmap, ADXL345_REG_POWER_CTL,
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ADXL345_POWER_CTL_STANDBY);
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}
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EXPORT_SYMBOL_GPL(adxl345_core_remove);
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MODULE_AUTHOR("Eva Rachel Retuya <eraretuya@gmail.com>");
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MODULE_DESCRIPTION("ADXL345 3-Axis Digital Accelerometer core driver");
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MODULE_LICENSE("GPL v2");
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