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a01ef59e13
The cfg_read/write functions are DesignWare-specific. Add dw_pcie prefix to avoid collision in global name space. Tested-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/*
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* Synopsys Designware PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _PCIE_DESIGNWARE_H
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#define _PCIE_DESIGNWARE_H
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struct pcie_port_info {
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u32 cfg0_size;
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u32 cfg1_size;
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u32 io_size;
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u32 mem_size;
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phys_addr_t io_bus_addr;
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phys_addr_t mem_bus_addr;
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};
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/*
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* Maximum number of MSI IRQs can be 256 per controller. But keep
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* it 32 as of now. Probably we will never need more than 32. If needed,
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* then increment it in multiple of 32.
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*/
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#define MAX_MSI_IRQS 32
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#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
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struct pcie_port {
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struct device *dev;
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u8 root_bus_nr;
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void __iomem *dbi_base;
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u64 cfg0_base;
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void __iomem *va_cfg0_base;
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u64 cfg1_base;
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void __iomem *va_cfg1_base;
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u64 io_base;
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u64 mem_base;
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spinlock_t conf_lock;
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struct resource cfg;
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struct resource io;
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struct resource mem;
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struct pcie_port_info config;
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int irq;
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u32 lanes;
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struct pcie_host_ops *ops;
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int msi_irq;
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struct irq_domain *irq_domain;
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unsigned long msi_data;
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DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
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};
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struct pcie_host_ops {
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void (*readl_rc)(struct pcie_port *pp,
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void __iomem *dbi_base, u32 *val);
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void (*writel_rc)(struct pcie_port *pp,
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u32 val, void __iomem *dbi_base);
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int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
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int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
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int (*link_up)(struct pcie_port *pp);
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void (*host_init)(struct pcie_port *pp);
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};
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int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
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int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
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void dw_handle_msi_irq(struct pcie_port *pp);
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void dw_pcie_msi_init(struct pcie_port *pp);
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int dw_pcie_link_up(struct pcie_port *pp);
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void dw_pcie_setup_rc(struct pcie_port *pp);
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int dw_pcie_host_init(struct pcie_port *pp);
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#endif /* _PCIE_DESIGNWARE_H */
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