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d345ea2892
The symbol is an orphan, get rid of it.
Fixes: 7d0857a54a ("ARC: [SMP] Disallow RTSC")
Signed-off-by: Richard Weinberger <richard@nod.at>
Acked-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
84 lines
2.3 KiB
Plaintext
84 lines
2.3 KiB
Plaintext
#
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# Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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menuconfig ARC_PLAT_FPGA_LEGACY
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bool "\"Legacy\" ARC FPGA dev Boards"
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select ISS_SMP_EXTN if SMP
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help
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Support for ARC development boards, provided by Synopsys.
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These are based on FPGA or ISS. e.g.
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- ARCAngel4
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- ML509
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- MetaWare ISS
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if ARC_PLAT_FPGA_LEGACY
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config ARC_BOARD_ANGEL4
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bool "ARC Angel4"
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default y
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help
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ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based)
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config ARC_BOARD_ML509
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bool "ML509"
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help
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ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based)
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config ISS_SMP_EXTN
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bool "ARC SMP Extensions (ISS Models only)"
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default n
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depends on SMP
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help
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SMP Extensions to ARC700, in a "simulation only" Model, supported in
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ARC ISS (Instruction Set Simulator).
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The SMP extensions include:
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-IDU (Interrupt Distribution Unit)
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-XTL (To enable CPU start/stop/set-PC for another CPU)
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It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND)
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config ARC_SERIAL_BAUD
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int "UART Baud rate"
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default "115200"
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depends on SERIAL_ARC || SERIAL_ARC_CONSOLE
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help
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Baud rate for the ARC UART
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menuconfig ARC_HAS_BVCI_LAT_UNIT
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bool "BVCI Bus Latency Unit"
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depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
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help
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IP to add artificial latency to BVCI Bus Based FPGA builds.
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The default latency (even worst case) for FPGA is non-realistic
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(~10 SDRAM, ~5 SSRAM).
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config BVCI_LAT_UNITS
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hex "Latency Unit(s) Bitmap"
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default "0x0"
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depends on ARC_HAS_BVCI_LAT_UNIT
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help
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There are multiple Latency Units corresponding to the many
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interfaces of the system bus arbiter (both CPU side as well as
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the peripheral side).
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To add latency to ALL memory transaction, choose Unit 0, otherwise
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for finer grainer - interface wise latency, specify a bitmap (1 bit
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per unit) of all units. e.g. 1,2,12 will be 0x1003
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Unit 0 - System Arb and Mem Controller
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Unit 1 - I$ and System Bus
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Unit 2 - D$ and System Bus
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..
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Unit 12 - IDE Disk controller and System Bus
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config BVCI_LAT_CYCLES
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int "Latency Value in cycles"
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range 0 63
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default "30"
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depends on ARC_HAS_BVCI_LAT_UNIT
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endif
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