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60d93f64a8
Add the power domains names for the mt8167 SoC.
Fixes: 207f13b419 ("soc: mediatek: pm-domains: Add support for mt8167")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
94 lines
2.5 KiB
C
94 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8167-power.h>
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#define MT8167_PWR_STATUS_MFG_2D BIT(24)
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#define MT8167_PWR_STATUS_MFG_ASYNC BIT(25)
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/*
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* MT8167 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
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[MT8167_POWER_DOMAIN_MM] = {
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.name = "mm",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
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MT8167_TOP_AXI_PROT_EN_MCU_MM),
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},
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8167_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8167_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8167_POWER_DOMAIN_MFG_ASYNC] = {
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.name = "mfg_async",
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.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
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.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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.bp_infracfg = {
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BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
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MT8167_TOP_AXI_PROT_EN_MFG_EMI),
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},
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},
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[MT8167_POWER_DOMAIN_MFG_2D] = {
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.name = "mfg_2d",
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.sta_mask = MT8167_PWR_STATUS_MFG_2D,
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.ctl_offs = SPM_MFG_2D_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8167_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8167_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = SPM_CONN_PWR_CON,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = 0,
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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.bp_infracfg = {
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BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
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MT8167_TOP_AXI_PROT_EN_CONN_MCU |
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MT8167_TOP_AXI_PROT_EN_MCU_CONN),
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},
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},
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};
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static const struct scpsys_soc_data mt8167_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8167,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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};
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#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
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