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521deea640
This enables or disables power saving on the PCIe bus when the wifi is in operation or not. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
333 lines
8.9 KiB
C
333 lines
8.9 KiB
C
/*
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* Broadcom specific AMBA
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* PCI Core
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*
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* Copyright 2005, 2011, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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/**************************************************
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* R/W ops.
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**************************************************/
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
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}
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static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
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}
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static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
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{
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u32 v;
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int i;
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
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BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= (phy << 4);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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udelay(10);
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for (i = 0; i < 200; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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usleep_range(1000, 2000);
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}
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}
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static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
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{
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int max_retries = 10;
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u16 ret = 0;
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u32 v;
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int i;
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_READ;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
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udelay(10);
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ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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break;
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}
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usleep_range(1000, 2000);
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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return ret;
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}
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static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
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u8 address, u16 data)
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{
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int max_retries = 10;
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u32 v;
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int i;
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= data;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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usleep_range(1000, 2000);
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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}
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static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
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u8 address, u16 data)
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{
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bcma_pcie_mdio_write(pc, device, address, data);
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return bcma_pcie_mdio_read(pc, device, address);
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}
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/**************************************************
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* Workarounds.
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**************************************************/
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static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
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{
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u32 tmp;
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tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
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if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
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return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
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BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
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else
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return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
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}
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static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
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{
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u16 tmp;
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bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
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BCMA_CORE_PCI_SERDES_RX_CTRL,
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bcma_pcicore_polarity_workaround(pc));
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tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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BCMA_CORE_PCI_SERDES_PLL_CTRL);
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if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
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bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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BCMA_CORE_PCI_SERDES_PLL_CTRL,
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tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
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}
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static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
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{
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struct bcma_device *core = pc->core;
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u16 val16, core_index;
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uint regoff;
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regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
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core_index = (u16)core->core_index;
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val16 = pcicore_read16(pc, regoff);
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if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
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!= core_index) {
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val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
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(val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
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pcicore_write16(pc, regoff, val16);
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}
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}
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/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
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/* Needs to happen when coming out of 'standby'/'hibernate' */
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static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
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{
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u16 val16;
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uint regoff;
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regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
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val16 = pcicore_read16(pc, regoff);
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if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
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val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
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pcicore_write16(pc, regoff, val16);
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}
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}
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static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up)
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{
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u16 data;
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if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
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data = up ? 0x74 : 0x7C;
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
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} else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
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data = up ? 0x75 : 0x7D;
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
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}
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}
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/**************************************************
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* Init.
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**************************************************/
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static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
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{
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bcma_core_pci_fixcfg(pc);
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bcma_pcicore_serdes_workaround(pc);
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bcma_core_pci_config_fixup(pc);
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}
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void bcma_core_pci_init(struct bcma_drv_pci *pc)
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{
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if (pc->setup_done)
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return;
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
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if (pc->hostmode)
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bcma_core_pci_hostmode_init(pc);
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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if (!pc->hostmode)
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bcma_core_pci_clientmode_init(pc);
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}
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int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
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bool enable)
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{
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struct pci_dev *pdev;
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u32 coremask, tmp;
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int err = 0;
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if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
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/* This bcma device is not on a PCI host-bus. So the IRQs are
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* not routed through the PCI core.
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* So we must not enable routing through the PCI core. */
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goto out;
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}
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pdev = pc->core->bus->host_pci;
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err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
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if (err)
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goto out;
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coremask = BIT(core->core_index) << 8;
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if (enable)
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tmp |= coremask;
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else
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tmp &= ~coremask;
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err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
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static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
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{
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u32 w;
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w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
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if (extend)
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w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
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else
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w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
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bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
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bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
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}
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void bcma_core_pci_up(struct bcma_bus *bus)
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{
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struct bcma_drv_pci *pc;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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return;
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pc = &bus->drv_pci[0];
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bcma_core_pci_power_save(pc, true);
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bcma_core_pci_extend_L1timer(pc, true);
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_up);
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void bcma_core_pci_down(struct bcma_bus *bus)
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{
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struct bcma_drv_pci *pc;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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return;
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pc = &bus->drv_pci[0];
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bcma_core_pci_extend_L1timer(pc, false);
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bcma_core_pci_power_save(pc, false);
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_down);
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