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01b9f4b0ed
Since the hardware only provides reporting for the last exception handled, and the values are valid only when executing the exception handler, we need to save the context for reporting at a later point. While we do this for one exception, it doesn't work properly when handling a second one as the original exception is clobbered by the double fault. So when double fault debugging is enabled, create a dedicated shadow of these values and save/restore out of there. Now the crash report properly displays the first exception as well as the second one. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
216 lines
4.1 KiB
ArmAsm
216 lines
4.1 KiB
ArmAsm
/*
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* File: arch/blackfin/mach-bf561/secondary.S
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* Based on: arch/blackfin/mach-bf561/head.S
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* Author: Philippe Gerum <rpm@xenomai.org>
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*
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* Copyright 2007 Analog Devices Inc.
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*
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* Description: BF561 coreB bootstrap file
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/asm-offsets.h>
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__INIT
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/* Lay the initial stack into the L1 scratch area of Core B */
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#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
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ENTRY(_coreb_trampoline_start)
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/* Set the SYSCFG register */
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R0 = 0x36;
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SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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R0 = 0;
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/*Clear Out All the data and pointer Registers*/
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R1 = R0;
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R2 = R0;
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R3 = R0;
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R4 = R0;
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R5 = R0;
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R6 = R0;
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R7 = R0;
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P0 = R0;
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P1 = R0;
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P2 = R0;
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P3 = R0;
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P4 = R0;
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P5 = R0;
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LC0 = r0;
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LC1 = r0;
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L0 = r0;
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L1 = r0;
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers*/
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B0 = r0;
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B1 = r0;
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B2 = r0;
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B3 = r0;
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I0 = r0;
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I1 = r0;
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I2 = r0;
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I3 = r0;
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M0 = r0;
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M1 = r0;
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M2 = r0;
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M3 = r0;
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/* Turn off the icache */
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p0.l = LO(IMEM_CONTROL);
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p0.h = HI(IMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENICPLB;
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R0 = R0 & R1;
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/* Anomaly 05000125 */
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#ifdef ANOMALY_05000125
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CLI R2;
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SSYNC;
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#endif
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[p0] = R0;
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SSYNC;
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#ifdef ANOMALY_05000125
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STI R2;
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#endif
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/* Turn off the dcache */
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p0.l = LO(DMEM_CONTROL);
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p0.h = HI(DMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENDCPLB;
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R0 = R0 & R1;
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/* Anomaly 05000125 */
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#ifdef ANOMALY_05000125
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CLI R2;
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SSYNC;
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#endif
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[p0] = R0;
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SSYNC;
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#ifdef ANOMALY_05000125
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STI R2;
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#endif
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/* in case of double faults, save a few things */
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p0.l = _init_retx_coreb;
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p0.h = _init_retx_coreb;
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R0 = RETX;
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[P0] = R0;
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#ifdef CONFIG_DEBUG_DOUBLEFAULT
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/* Only save these if we are storing them,
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* This happens here, since L1 gets clobbered
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* below
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*/
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GET_PDA(p0, r0);
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r7 = [p0 + PDA_DF_RETX];
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p1.l = _init_saved_retx_coreb;
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p1.h = _init_saved_retx_coreb;
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[p1] = r7;
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r7 = [p0 + PDA_DF_DCPLB];
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p1.l = _init_saved_dcplb_fault_addr_coreb;
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p1.h = _init_saved_dcplb_fault_addr_coreb;
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[p1] = r7;
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r7 = [p0 + PDA_DF_ICPLB];
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p1.l = _init_saved_icplb_fault_addr_coreb;
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p1.h = _init_saved_icplb_fault_addr_coreb;
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[p1] = r7;
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r7 = [p0 + PDA_DF_SEQSTAT];
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p1.l = _init_saved_seqstat_coreb;
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p1.h = _init_saved_seqstat_coreb;
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[p1] = r7;
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#endif
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/* Initialize stack pointer */
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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/* This section keeps the processor in supervisor mode
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* during core B startup. Branches to the idle task.
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*/
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/* EVT15 = _real_start */
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p0.l = lo(EVT15);
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p0.h = hi(EVT15);
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p1.l = _coreb_start;
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p1.h = _coreb_start;
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[p0] = p1;
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csync;
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p0.l = lo(IMASK);
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p0.h = hi(IMASK);
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p1.l = IMASK_IVG15;
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p1.h = 0x0;
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[p0] = p1;
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csync;
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raise 15;
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p0.l = .LWAIT_HERE;
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p0.h = .LWAIT_HERE;
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reti = p0;
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#if defined(ANOMALY_05000281)
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nop; nop; nop;
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#endif
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rti;
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.LWAIT_HERE:
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jump .LWAIT_HERE;
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ENDPROC(_coreb_trampoline_start)
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ENTRY(_coreb_trampoline_end)
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ENTRY(_coreb_start)
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[--sp] = reti;
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p0.l = lo(WDOGB_CTL);
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p0.h = hi(WDOGB_CTL);
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r0 = 0xAD6(z);
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w[p0] = r0; /* Clear the watchdog. */
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ssync;
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/*
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* switch to IDLE stack.
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*/
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p0.l = _secondary_stack;
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p0.h = _secondary_stack;
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sp = [p0];
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usp = sp;
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fp = sp;
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sp += -12;
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call _init_pda
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sp += 12;
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call _secondary_start_kernel;
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.L_exit:
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jump.s .L_exit;
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ENDPROC(_coreb_start)
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__FINIT
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