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d41ced01f2
Adds support for the FALCON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
91 lines
2.1 KiB
C
91 lines
2.1 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pm.h>
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#include <asm/reboot.h>
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#include <linux/export.h>
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#include <lantiq_soc.h>
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/* CPU0 Reset Source Register */
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#define SYS1_CPU0RS 0x0040
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/* reset cause mask */
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#define CPU0RS_MASK 0x0003
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/* CPU0 Boot Mode Register */
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#define SYS1_BM 0x00a0
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/* boot mode mask */
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#define BM_MASK 0x0005
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/* allow platform code to find out what surce we booted from */
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unsigned char ltq_boot_select(void)
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{
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return ltq_sys1_r32(SYS1_BM) & BM_MASK;
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}
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/* allow the watchdog driver to find out what the boot reason was */
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int ltq_reset_cause(void)
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{
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return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
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}
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EXPORT_SYMBOL_GPL(ltq_reset_cause);
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#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
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#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
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#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
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#define BOOT_PW1 0x4C545100
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#define BOOT_PW2 0x0051544C
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#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
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#define WDT_PW1 0x00BE0000
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#define WDT_PW2 0x00DC0000
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static void machine_restart(char *command)
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{
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local_irq_disable();
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/* reboot magic */
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ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
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ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
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ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
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/* watchdog magic */
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ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
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ltq_w32(WDT_PW2 |
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(0x3 << 26) | /* PWL */
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(0x2 << 24) | /* CLKDIV */
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(0x1 << 31) | /* enable */
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(1), /* reload */
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(void *)WDT_REG_BASE);
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unreachable();
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}
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static void machine_halt(void)
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{
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local_irq_disable();
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unreachable();
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}
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static void machine_power_off(void)
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{
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local_irq_disable();
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unreachable();
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}
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static int __init mips_reboot_setup(void)
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{
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_machine_restart = machine_restart;
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_machine_halt = machine_halt;
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pm_power_off = machine_power_off;
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return 0;
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}
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arch_initcall(mips_reboot_setup);
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