Chen Lifu c08b4848f5 riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit ... Since commit 5d8544e2d0 ("RISC-V: Generic library routines and assembly") and commit ebcbd75e39 ("riscv: Fix the bug in memory access fixup code"), if __clear_user and __copy_user return from an fixup branch, CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that S-mode memory accesses to pages that are accessible by U-mode will success. Disable S-mode access to U-mode memory should clear SR_SUM bit. Fixes: 5d8544e2d0 ("RISC-V: Generic library routines and assembly") Fixes: ebcbd75e39 ("riscv: Fix the bug in memory access fixup code") Signed-off-by: Chen Lifu <chenlifu@huawei.com> Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk> Link: https://lore.kernel.org/r/20220615014714.1650349-1-chenlifu@huawei.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-08-10 14:06:31 -07:00
..
delay.c	include/linux/delay.h: replace kernel.h with the necessary inclusions	2021-11-09 10:02:49 -08:00
error-inject.c	riscv: Add support for function error injection	2021-01-14 15:09:09 -08:00
Makefile	riscv: Add support for function error injection	2021-01-14 15:09:09 -08:00
memcpy.S	riscv: Add KASAN support	2020-01-22 13:09:58 -08:00
memmove.S	riscv: Fixed misaligned memory access. Fixed pointer comparison.	2022-03-10 10:24:04 -08:00
memset.S	riscv: Add KASAN support	2020-01-22 13:09:58 -08:00
tishift.S	riscv: Less inefficient gcc tishift helpers (and export their symbols)	2020-01-18 19:13:41 -08:00
uaccess.S	riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit	2022-08-10 14:06:31 -07:00