mirror of
https://github.com/torvalds/linux.git
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c153f45f9b
The data is now in kernel space, copied in/out as appropriate according to t
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures. This also means that XFree86 4.2.0 support for i810 DR
is lost.
Signed-off-by: Dave Airlie <airlied@linux.ie>
576 lines
19 KiB
C
576 lines
19 KiB
C
/* savage_drv.h -- Private header for the savage driver */
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/*
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* Copyright 2004 Felix Kuehling
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __SAVAGE_DRV_H__
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#define __SAVAGE_DRV_H__
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#define DRIVER_AUTHOR "Felix Kuehling"
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#define DRIVER_NAME "savage"
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#define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]"
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#define DRIVER_DATE "20050313"
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#define DRIVER_MAJOR 2
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#define DRIVER_MINOR 4
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#define DRIVER_PATCHLEVEL 1
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/* Interface history:
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*
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* 1.x The DRM driver from the VIA/S3 code drop, basically a dummy
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* 2.0 The first real DRM
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* 2.1 Scissors registers managed by the DRM, 3D operations clipped by
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* cliprects of the cmdbuf ioctl
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* 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX
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* 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits
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* wide and thus very long lived (unlikely to ever wrap). The size
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* in the struct was 32 bits before, but only 16 bits were used
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* 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is
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* actually used
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*/
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typedef struct drm_savage_age {
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uint16_t event;
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unsigned int wrap;
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} drm_savage_age_t;
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typedef struct drm_savage_buf_priv {
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struct drm_savage_buf_priv *next;
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struct drm_savage_buf_priv *prev;
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drm_savage_age_t age;
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struct drm_buf *buf;
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} drm_savage_buf_priv_t;
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typedef struct drm_savage_dma_page {
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drm_savage_age_t age;
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unsigned int used, flushed;
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} drm_savage_dma_page_t;
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#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */
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/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
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* size of 16kbytes or 4k entries. Minimum requirement would be
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* 10kbytes for 255 40-byte vertices in one drawing command. */
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#define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4)
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/* interesting bits of hardware state that are saved in dev_priv */
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typedef union {
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struct drm_savage_common_state {
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uint32_t vbaddr;
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} common;
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struct {
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unsigned char pad[sizeof(struct drm_savage_common_state)];
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uint32_t texctrl, texaddr;
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uint32_t scstart, new_scstart;
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uint32_t scend, new_scend;
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} s3d;
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struct {
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unsigned char pad[sizeof(struct drm_savage_common_state)];
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uint32_t texdescr, texaddr0, texaddr1;
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uint32_t drawctrl0, new_drawctrl0;
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uint32_t drawctrl1, new_drawctrl1;
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} s4;
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} drm_savage_state_t;
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/* these chip tags should match the ones in the 2D driver in savage_regs.h. */
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enum savage_family {
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S3_UNKNOWN = 0,
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S3_SAVAGE3D,
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S3_SAVAGE_MX,
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S3_SAVAGE4,
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S3_PROSAVAGE,
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S3_TWISTER,
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S3_PROSAVAGEDDR,
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S3_SUPERSAVAGE,
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S3_SAVAGE2000,
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S3_LAST
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};
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extern struct drm_ioctl_desc savage_ioctls[];
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extern int savage_max_ioctl;
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#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
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#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
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|| (chip==S3_PROSAVAGE) \
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|| (chip==S3_TWISTER) \
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|| (chip==S3_PROSAVAGEDDR))
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#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
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#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
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#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \
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||(chip==S3_PROSAVAGEDDR))
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/* flags */
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#define SAVAGE_IS_AGP 1
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typedef struct drm_savage_private {
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drm_savage_sarea_t *sarea_priv;
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drm_savage_buf_priv_t head, tail;
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/* who am I? */
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enum savage_family chipset;
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unsigned int cob_size;
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unsigned int bci_threshold_lo, bci_threshold_hi;
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unsigned int dma_type;
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/* frame buffer layout */
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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/* bitmap descriptors for swap and clear */
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unsigned int front_bd, back_bd, depth_bd;
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/* local textures */
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unsigned int texture_offset;
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unsigned int texture_size;
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/* memory regions in physical memory */
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drm_local_map_t *sarea;
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drm_local_map_t *mmio;
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drm_local_map_t *fb;
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drm_local_map_t *aperture;
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drm_local_map_t *status;
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drm_local_map_t *agp_textures;
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drm_local_map_t *cmd_dma;
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drm_local_map_t fake_dma;
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struct {
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int handle;
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unsigned long base, size;
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} mtrr[3];
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/* BCI and status-related stuff */
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volatile uint32_t *status_ptr, *bci_ptr;
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uint32_t status_used_mask;
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uint16_t event_counter;
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unsigned int event_wrap;
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/* Savage4 command DMA */
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drm_savage_dma_page_t *dma_pages;
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unsigned int nr_dma_pages, first_dma_page, current_dma_page;
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drm_savage_age_t last_dma_age;
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/* saved hw state for global/local check on S3D */
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uint32_t hw_draw_ctrl, hw_zbuf_ctrl;
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/* and for scissors (global, so don't emit if not changed) */
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uint32_t hw_scissors_start, hw_scissors_end;
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drm_savage_state_t state;
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/* after emitting a wait cmd Savage3D needs 63 nops before next DMA */
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unsigned int waiting;
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/* config/hardware-dependent function pointers */
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int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n);
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int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e);
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/* Err, there is a macro wait_event in include/linux/wait.h.
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* Avoid unwanted macro expansion. */
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void (*emit_clip_rect) (struct drm_savage_private * dev_priv,
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const struct drm_clip_rect * pbox);
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void (*dma_flush) (struct drm_savage_private * dev_priv);
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} drm_savage_private_t;
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/* ioctls */
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extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv);
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extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
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/* BCI functions */
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extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
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unsigned int flags);
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extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf);
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extern void savage_dma_reset(drm_savage_private_t * dev_priv);
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extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page);
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extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv,
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unsigned int n);
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extern int savage_driver_load(struct drm_device *dev, unsigned long chipset);
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extern int savage_driver_firstopen(struct drm_device *dev);
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extern void savage_driver_lastclose(struct drm_device *dev);
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extern int savage_driver_unload(struct drm_device *dev);
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extern void savage_reclaim_buffers(struct drm_device *dev,
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struct drm_file *file_priv);
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/* state functions */
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extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv,
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const struct drm_clip_rect * pbox);
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extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv,
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const struct drm_clip_rect * pbox);
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#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
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#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
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#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
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#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
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#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
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#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
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* inside the MMIO region */
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#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip
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* BCI FIFO */
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/*
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* MMIO registers
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*/
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#define SAVAGE_STATUS_WORD0 0x48C00
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#define SAVAGE_STATUS_WORD1 0x48C04
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#define SAVAGE_ALT_STATUS_WORD0 0x48C60
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#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
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#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
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/* Copied from savage_bci.h in the 2D driver with some renaming. */
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/* Bitmap descriptors */
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#define SAVAGE_BD_STRIDE_SHIFT 0
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#define SAVAGE_BD_BPP_SHIFT 16
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#define SAVAGE_BD_TILE_SHIFT 24
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#define SAVAGE_BD_BW_DISABLE (1<<28)
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/* common: */
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#define SAVAGE_BD_TILE_LINEAR 0
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/* savage4, MX, IX, 3D */
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#define SAVAGE_BD_TILE_16BPP 2
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#define SAVAGE_BD_TILE_32BPP 3
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/* twister, prosavage, DDR, supersavage, 2000 */
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#define SAVAGE_BD_TILE_DEST 1
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#define SAVAGE_BD_TILE_TEXTURE 2
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/* GBD - BCI enable */
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/* savage4, MX, IX, 3D */
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#define SAVAGE_GBD_BCI_ENABLE 8
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/* twister, prosavage, DDR, supersavage, 2000 */
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#define SAVAGE_GBD_BCI_ENABLE_TWISTER 0
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#define SAVAGE_GBD_BIG_ENDIAN 4
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#define SAVAGE_GBD_LITTLE_ENDIAN 0
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#define SAVAGE_GBD_64 1
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/* Global Bitmap Descriptor */
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#define SAVAGE_BCI_GLB_BD_LOW 0x8168
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#define SAVAGE_BCI_GLB_BD_HIGH 0x816C
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/*
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* BCI registers
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*/
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/* Savage4/Twister/ProSavage 3D registers */
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#define SAVAGE_DRAWLOCALCTRL_S4 0x1e
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#define SAVAGE_TEXPALADDR_S4 0x1f
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#define SAVAGE_TEXCTRL0_S4 0x20
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#define SAVAGE_TEXCTRL1_S4 0x21
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#define SAVAGE_TEXADDR0_S4 0x22
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#define SAVAGE_TEXADDR1_S4 0x23
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#define SAVAGE_TEXBLEND0_S4 0x24
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#define SAVAGE_TEXBLEND1_S4 0x25
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#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */
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#define SAVAGE_TEXDESCR_S4 0x27
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#define SAVAGE_FOGTABLE_S4 0x28
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#define SAVAGE_FOGCTRL_S4 0x30
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#define SAVAGE_STENCILCTRL_S4 0x31
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#define SAVAGE_ZBUFCTRL_S4 0x32
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#define SAVAGE_ZBUFOFF_S4 0x33
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#define SAVAGE_DESTCTRL_S4 0x34
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#define SAVAGE_DRAWCTRL0_S4 0x35
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#define SAVAGE_DRAWCTRL1_S4 0x36
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#define SAVAGE_ZWATERMARK_S4 0x37
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#define SAVAGE_DESTTEXRWWATERMARK_S4 0x38
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#define SAVAGE_TEXBLENDCOLOR_S4 0x39
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/* Savage3D/MX/IX 3D registers */
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#define SAVAGE_TEXPALADDR_S3D 0x18
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#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */
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#define SAVAGE_TEXADDR_S3D 0x1A
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#define SAVAGE_TEXDESCR_S3D 0x1B
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#define SAVAGE_TEXCTRL_S3D 0x1C
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#define SAVAGE_FOGTABLE_S3D 0x20
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#define SAVAGE_FOGCTRL_S3D 0x30
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#define SAVAGE_DRAWCTRL_S3D 0x31
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#define SAVAGE_ZBUFCTRL_S3D 0x32
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#define SAVAGE_ZBUFOFF_S3D 0x33
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#define SAVAGE_DESTCTRL_S3D 0x34
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#define SAVAGE_SCSTART_S3D 0x35
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#define SAVAGE_SCEND_S3D 0x36
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#define SAVAGE_ZWATERMARK_S3D 0x37
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#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
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/* common stuff */
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#define SAVAGE_VERTBUFADDR 0x3e
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#define SAVAGE_BITPLANEWTMASK 0xd7
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#define SAVAGE_DMABUFADDR 0x51
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/* texture enable bits (needed for tex addr checking) */
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#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */
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#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */
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#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */
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/* Global fields in Savage4/Twister/ProSavage 3D registers:
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*
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* All texture registers and DrawLocalCtrl are local. All other
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* registers are global. */
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/* Global fields in Savage3D/MX/IX 3D registers:
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*
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* All texture registers are local. DrawCtrl and ZBufCtrl are
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* partially local. All other registers are global.
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*
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* DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal
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* ZBufCtrl global fields: zCmpFunc, zBufEn
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*/
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#define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c
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#define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027
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/* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d)
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*/
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#define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff
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#define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff
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/*
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* BCI commands
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*/
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#define BCI_CMD_NOP 0x40000000
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#define BCI_CMD_RECT 0x48000000
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#define BCI_CMD_RECT_XP 0x01000000
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#define BCI_CMD_RECT_YP 0x02000000
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#define BCI_CMD_SCANLINE 0x50000000
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#define BCI_CMD_LINE 0x5C000000
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#define BCI_CMD_LINE_LAST_PIXEL 0x58000000
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#define BCI_CMD_BYTE_TEXT 0x63000000
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#define BCI_CMD_NT_BYTE_TEXT 0x67000000
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#define BCI_CMD_BIT_TEXT 0x6C000000
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#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
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#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
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#define BCI_CMD_SEND_COLOR 0x00008000
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#define BCI_CMD_CLIP_NONE 0x00000000
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#define BCI_CMD_CLIP_CURRENT 0x00002000
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#define BCI_CMD_CLIP_LR 0x00004000
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#define BCI_CMD_CLIP_NEW 0x00006000
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#define BCI_CMD_DEST_GBD 0x00000000
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#define BCI_CMD_DEST_PBD 0x00000800
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#define BCI_CMD_DEST_PBD_NEW 0x00000C00
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#define BCI_CMD_DEST_SBD 0x00001000
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#define BCI_CMD_DEST_SBD_NEW 0x00001400
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#define BCI_CMD_SRC_TRANSPARENT 0x00000200
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#define BCI_CMD_SRC_SOLID 0x00000000
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#define BCI_CMD_SRC_GBD 0x00000020
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#define BCI_CMD_SRC_COLOR 0x00000040
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#define BCI_CMD_SRC_MONO 0x00000060
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#define BCI_CMD_SRC_PBD_COLOR 0x00000080
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#define BCI_CMD_SRC_PBD_MONO 0x000000A0
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#define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0
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#define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0
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#define BCI_CMD_SRC_SBD_COLOR 0x00000100
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#define BCI_CMD_SRC_SBD_MONO 0x00000120
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#define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140
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#define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160
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#define BCI_CMD_PAT_TRANSPARENT 0x00000010
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#define BCI_CMD_PAT_NONE 0x00000000
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#define BCI_CMD_PAT_COLOR 0x00000002
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#define BCI_CMD_PAT_MONO 0x00000003
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#define BCI_CMD_PAT_PBD_COLOR 0x00000004
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#define BCI_CMD_PAT_PBD_MONO 0x00000005
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#define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006
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#define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007
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#define BCI_CMD_PAT_SBD_COLOR 0x00000008
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#define BCI_CMD_PAT_SBD_MONO 0x00000009
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#define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A
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#define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B
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#define BCI_BD_BW_DISABLE 0x10000000
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#define BCI_BD_TILE_MASK 0x03000000
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#define BCI_BD_TILE_NONE 0x00000000
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#define BCI_BD_TILE_16 0x02000000
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#define BCI_BD_TILE_32 0x03000000
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#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF)
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#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
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#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF)
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#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
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#define BCI_CMD_SET_REGISTER 0x96000000
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#define BCI_CMD_WAIT 0xC0000000
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#define BCI_CMD_WAIT_3D 0x00010000
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#define BCI_CMD_WAIT_2D 0x00020000
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#define BCI_CMD_UPDATE_EVENT_TAG 0x98000000
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#define BCI_CMD_DRAW_PRIM 0x80000000
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#define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000
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#define BCI_CMD_DRAW_CONT 0x01000000
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#define BCI_CMD_DRAW_TRILIST 0x00000000
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#define BCI_CMD_DRAW_TRISTRIP 0x02000000
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#define BCI_CMD_DRAW_TRIFAN 0x04000000
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#define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff
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#define BCI_CMD_DRAW_NO_Z 0x00000001
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#define BCI_CMD_DRAW_NO_W 0x00000002
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#define BCI_CMD_DRAW_NO_CD 0x00000004
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#define BCI_CMD_DRAW_NO_CS 0x00000008
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#define BCI_CMD_DRAW_NO_U0 0x00000010
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#define BCI_CMD_DRAW_NO_V0 0x00000020
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#define BCI_CMD_DRAW_NO_UV0 0x00000030
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#define BCI_CMD_DRAW_NO_U1 0x00000040
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#define BCI_CMD_DRAW_NO_V1 0x00000080
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#define BCI_CMD_DRAW_NO_UV1 0x000000c0
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#define BCI_CMD_DMA 0xa8000000
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#define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF)
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#define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF)
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#define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF)
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#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
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#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
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#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
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#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF))
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#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF))
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#define BCI_LINE_MISC(maj, ym, xp, yp, err) \
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(((maj) & 0x1FFF) | \
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((ym) ? 1<<13 : 0) | \
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((xp) ? 1<<14 : 0) | \
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((yp) ? 1<<15 : 0) | \
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((err) << 16))
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/*
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* common commands
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*/
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#define BCI_SET_REGISTERS( first, n ) \
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BCI_WRITE(BCI_CMD_SET_REGISTER | \
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((uint32_t)(n) & 0xff) << 16 | \
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((uint32_t)(first) & 0xffff))
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#define DMA_SET_REGISTERS( first, n ) \
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DMA_WRITE(BCI_CMD_SET_REGISTER | \
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((uint32_t)(n) & 0xff) << 16 | \
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((uint32_t)(first) & 0xffff))
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#define BCI_DRAW_PRIMITIVE(n, type, skip) \
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BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
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((n) << 16))
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#define DMA_DRAW_PRIMITIVE(n, type, skip) \
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DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
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((n) << 16))
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#define BCI_DRAW_INDICES_S3D(n, type, i0) \
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BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
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((n) << 16) | (i0))
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#define BCI_DRAW_INDICES_S4(n, type, skip) \
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BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
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(skip) | ((n) << 16))
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#define BCI_DMA(n) \
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BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1))
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/*
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* access to MMIO
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*/
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#define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
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#define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
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/*
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* access to the burst command interface (BCI)
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*/
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#define SAVAGE_BCI_DEBUG 1
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#define BCI_LOCALS volatile uint32_t *bci_ptr;
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#define BEGIN_BCI( n ) do { \
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dev_priv->wait_fifo(dev_priv, (n)); \
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bci_ptr = dev_priv->bci_ptr; \
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} while(0)
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#define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val)
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/*
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* command DMA support
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*/
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#define SAVAGE_DMA_DEBUG 1
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#define DMA_LOCALS uint32_t *dma_ptr;
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#define BEGIN_DMA( n ) do { \
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unsigned int cur = dev_priv->current_dma_page; \
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unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \
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dev_priv->dma_pages[cur].used; \
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if ((n) > rest) { \
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dma_ptr = savage_dma_alloc(dev_priv, (n)); \
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} else { /* fast path for small allocations */ \
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dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \
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cur * SAVAGE_DMA_PAGE_SIZE + \
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dev_priv->dma_pages[cur].used; \
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if (dev_priv->dma_pages[cur].used == 0) \
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savage_dma_wait(dev_priv, cur); \
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dev_priv->dma_pages[cur].used += (n); \
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} \
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} while(0)
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#define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val)
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#define DMA_COPY(src, n) do { \
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memcpy(dma_ptr, (src), (n)*4); \
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dma_ptr += n; \
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} while(0)
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#if SAVAGE_DMA_DEBUG
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#define DMA_COMMIT() do { \
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unsigned int cur = dev_priv->current_dma_page; \
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uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \
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cur * SAVAGE_DMA_PAGE_SIZE + \
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dev_priv->dma_pages[cur].used; \
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if (dma_ptr != expected) { \
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DRM_ERROR("DMA allocation and use don't match: " \
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|
"%p != %p\n", expected, dma_ptr); \
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|
savage_dma_reset(dev_priv); \
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} \
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} while(0)
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#else
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#define DMA_COMMIT() do {/* nothing */} while(0)
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#endif
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|
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#define DMA_FLUSH() dev_priv->dma_flush(dev_priv)
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|
|
/* Buffer aging via event tag
|
|
*/
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|
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#define UPDATE_EVENT_COUNTER( ) do { \
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if (dev_priv->status_ptr) { \
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|
uint16_t count; \
|
|
/* coordinate with Xserver */ \
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|
count = dev_priv->status_ptr[1023]; \
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|
if (count < dev_priv->event_counter) \
|
|
dev_priv->event_wrap++; \
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|
dev_priv->event_counter = count; \
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|
} \
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} while(0)
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|
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#define SET_AGE( age, e, w ) do { \
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|
(age)->event = e; \
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|
(age)->wrap = w; \
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} while(0)
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|
|
#define TEST_AGE( age, e, w ) \
|
|
( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
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#endif /* __SAVAGE_DRV_H__ */
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