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2c7a5c5c48
openrisc qemu tests fail with the following crash.
Unable to handle kernel access at virtual address 0xc0300c34
Oops#: 0001
CPU #: 0
PC: c016c710 SR: 0000ae67 SP: c1017e04
GPR00: 00000000 GPR01: c1017e04 GPR02: c0300c34 GPR03: c0300c34
GPR04: 00000000 GPR05: c0300cb0 GPR06: c0300c34 GPR07: 000000ff
GPR08: c107f074 GPR09: c0199ef4 GPR10: c1016000 GPR11: 00000000
GPR12: 00000000 GPR13: c107f044 GPR14: c0473774 GPR15: 07ce0000
GPR16: 00000000 GPR17: c107ed8a GPR18: 00009600 GPR19: c107f044
GPR20: c107ee74 GPR21: 00000003 GPR22: c0473770 GPR23: 00000033
GPR24: 000000bf GPR25: 00000019 GPR26: c046400c GPR27: 00000001
GPR28: c0464028 GPR29: c1018000 GPR30: 00000006 GPR31: ccf37483
RES: 00000000 oGPR11: ffffffff
Process swapper (pid: 1, stackpage=c1001960)
Stack: Stack dump [0xc1017cf8]:
sp + 00: 0xc1017e04
sp + 04: 0xc0300c34
sp + 08: 0xc0300c34
sp + 12: 0x00000000
...
Bisect points to commit
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| .. | ||
| boot/dts | ||
| configs | ||
| include | ||
| kernel | ||
| lib | ||
| mm | ||
| Kconfig | ||
| Makefile | ||
| README.openrisc | ||
| TODO.openrisc | ||
OpenRISC Linux
==============
This is a port of Linux to the OpenRISC class of microprocessors; the initial
target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
For information about OpenRISC processors and ongoing development:
website http://openrisc.net
For more information about Linux on OpenRISC, please contact South Pole AB.
email: info@southpole.se
website: http://southpole.se
http://southpoleconsulting.com
---------------------------------------------------------------------
Build instructions for OpenRISC toolchain and Linux
===================================================
In order to build and run Linux for OpenRISC, you'll need at least a basic
toolchain and, perhaps, the architectural simulator. Steps to get these bits
in place are outlined here.
1) The toolchain can be obtained from openrisc.net. Instructions for building
a toolchain can be found at:
http://openrisc.net/toolchain-build.html
2) or1ksim (optional)
or1ksim is the architectural simulator which will allow you to actually run
your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
git clone git://openrisc.net/jonas/or1ksim-svn
cd or1ksim
./configure --prefix=$OPENRISC_PREFIX
make
make install
3) Linux kernel
Build the kernel as usual
make ARCH=openrisc defconfig
make ARCH=openrisc
4) Run in architectural simulator
Grab the or1ksim platform configuration file (from the or1ksim source) and
together with your freshly built vmlinux, run your kernel with the following
incantation:
sim -f arch/openrisc/or1ksim.cfg vmlinux
---------------------------------------------------------------------
Terminology
===========
In the code, the following particles are used on symbols to limit the scope
to more or less specific processor implementations:
openrisc: the OpenRISC class of processors
or1k: the OpenRISC 1000 family of processors
or1200: the OpenRISC 1200 processor
---------------------------------------------------------------------
History
========
18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com)
initial port of linux to OpenRISC/or32 architecture.
all the core stuff is implemented and seams usable.
08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com)
complete change of TLB miss handling.
rewrite of exceptions handling.
fully functional sash-3.6 in default initrd.
a much improved version with changes all around.
10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com)
alot of bugfixes all over.
ethernet support, functional http and telnet servers.
running many standard linux apps.
26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com)
port to 2.6.x
30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com)
lots of bugfixes and enhancments.
added opencores framebuffer driver.
09. 10. 2010 Jonas Bonn (jonas@southpole.se)
major rewrite to bring up to par with upstream Linux 2.6.36