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a27fa58117
at91_set_serial_console is used to define the default console of linux. This is already manage by the cmdline. And if the boot loader can not be modified you can still set it by enabling the CONFIG_CMDLINE_EXTEND option. And then the command-line arguments provided by the boot loader will be appended to the default kernel command string. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
379 lines
9.7 KiB
C
379 lines
9.7 KiB
C
/*
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* arch/arm/mach-at91/at91rm9200.c
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*
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* Copyright (C) 2005 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include <mach/at91rm9200.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_st.h>
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#include <mach/cpu.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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static struct map_desc at91rm9200_io_desc[] __initdata = {
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{
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.virtual = AT91_VA_BASE_EMAC,
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.pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
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.length = SZ_16K,
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.type = MT_DEVICE,
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},
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91RM9200_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91RM9200_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ether_clk = {
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.name = "ether_clk",
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.pmc_mask = 1 << AT91RM9200_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91RM9200_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91RM9200_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91RM9200_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91RM9200_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91RM9200_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi_clk = {
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.name = "spi_clk",
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.pmc_mask = 1 << AT91RM9200_ID_SPI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91RM9200_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91RM9200_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91RM9200_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioD_clk = {
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.name = "pioD_clk",
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.pmc_mask = 1 << AT91RM9200_ID_PIOD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91RM9200_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91RM9200_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc2_clk = {
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.name = "ssc2_clk",
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.pmc_mask = 1 << AT91RM9200_ID_SSC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc3_clk = {
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.name = "tc3_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TC3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc4_clk = {
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.name = "tc4_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TC4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc5_clk = {
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.name = "tc5_clk",
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.pmc_mask = 1 << AT91RM9200_ID_TC5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioD_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc_clk,
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&udc_clk,
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&twi_clk,
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&spi_clk,
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&ssc0_clk,
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&ssc1_clk,
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&ssc2_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&tc3_clk,
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&tc4_clk,
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&tc5_clk,
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&ohci_clk,
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ðer_clk,
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// irq0 .. irq6
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
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/* fake hclk clock */
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CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
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CLKDEV_CON_ID("pioA", &pioA_clk),
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CLKDEV_CON_ID("pioB", &pioB_clk),
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CLKDEV_CON_ID("pioC", &pioC_clk),
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CLKDEV_CON_ID("pioD", &pioD_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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};
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/*
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* The four programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 2,
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};
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static struct clk pck3 = {
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.name = "pck3",
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.pmc_mask = AT91_PMC_PCK3,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 3,
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};
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static void __init at91rm9200_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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clk_register(&pck2);
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clk_register(&pck3);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
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{
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.id = AT91RM9200_ID_PIOA,
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.regbase = AT91RM9200_BASE_PIOA,
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}, {
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.id = AT91RM9200_ID_PIOB,
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.regbase = AT91RM9200_BASE_PIOB,
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}, {
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.id = AT91RM9200_ID_PIOC,
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.regbase = AT91RM9200_BASE_PIOC,
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}, {
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.id = AT91RM9200_ID_PIOD,
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.regbase = AT91RM9200_BASE_PIOD,
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}
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};
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static void at91rm9200_idle(void)
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{
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/*
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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}
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static void at91rm9200_restart(char mode, const char *cmd)
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{
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/*
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* Perform a hardware reset with the use of the Watchdog timer.
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*/
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at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
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at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
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}
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/* --------------------------------------------------------------------
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* AT91RM9200 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91rm9200_map_io(void)
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{
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/* Map peripherals */
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at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
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iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
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}
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static void __init at91rm9200_ioremap_registers(void)
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{
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at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
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at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
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}
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static void __init at91rm9200_initialize(void)
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{
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arm_pm_idle = at91rm9200_idle;
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arm_pm_restart = at91rm9200_restart;
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at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
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| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
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| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
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| (1 << AT91RM9200_ID_IRQ6);
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/* Initialize GPIO subsystem */
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at91_gpio_init(at91rm9200_gpio,
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cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface */
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2, /* USB Device Port */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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4, /* Serial Synchronous Controller 2 */
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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0, /* Timer Counter 3 */
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0, /* Timer Counter 4 */
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0, /* Timer Counter 5 */
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2, /* USB Host port */
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3, /* Ethernet MAC */
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0, /* Advanced Interrupt Controller (IRQ0) */
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0, /* Advanced Interrupt Controller (IRQ1) */
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0, /* Advanced Interrupt Controller (IRQ2) */
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0, /* Advanced Interrupt Controller (IRQ3) */
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0, /* Advanced Interrupt Controller (IRQ4) */
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0, /* Advanced Interrupt Controller (IRQ5) */
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0 /* Advanced Interrupt Controller (IRQ6) */
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};
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struct at91_init_soc __initdata at91rm9200_soc = {
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.map_io = at91rm9200_map_io,
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.default_irq_priority = at91rm9200_default_irq_priority,
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.ioremap_registers = at91rm9200_ioremap_registers,
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.register_clocks = at91rm9200_register_clocks,
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.init = at91rm9200_initialize,
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};
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