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1d8e64f40b
The flash ID is the new primary key into our database. Sort the entry by it. Keep the most specific ones first, because there might be ID collisions between shorter and longer ones. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-33-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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gd25q256_post_bfpt(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* GD25Q256C supports the first version of JESD216 which does not define
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* the Quad Enable methods. Overwrite the default Quad Enable method.
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*
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* GD25Q256 GENERATION | SFDP MAJOR VERSION | SFDP MINOR VERSION
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* GD25Q256C | SFDP_JESD216_MAJOR | SFDP_JESD216_MINOR
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* GD25Q256D | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
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* GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
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*/
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if (bfpt_header->major == SFDP_JESD216_MAJOR &&
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bfpt_header->minor == SFDP_JESD216_MINOR)
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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return 0;
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}
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static const struct spi_nor_fixups gd25q256_fixups = {
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.post_bfpt = gd25q256_post_bfpt,
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};
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static const struct flash_info gigadevice_nor_parts[] = {
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{
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.id = SNOR_ID(0xc8, 0x40, 0x15),
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.name = "gd25q16",
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.size = SZ_2M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xc8, 0x40, 0x16),
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.name = "gd25q32",
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.size = SZ_4M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xc8, 0x40, 0x17),
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.name = "gd25q64",
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.size = SZ_8M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xc8, 0x40, 0x18),
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.name = "gd25q128",
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.size = SZ_16M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xc8, 0x40, 0x19),
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.name = "gd25q256",
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
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.fixups = &gd25q256_fixups,
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.fixup_flags = SPI_NOR_4B_OPCODES,
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}, {
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.id = SNOR_ID(0xc8, 0x60, 0x16),
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.name = "gd25lq32",
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.size = SZ_4M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xc8, 0x60, 0x17),
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.name = "gd25lq64c",
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.size = SZ_8M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xc8, 0x60, 0x18),
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.name = "gd25lq128d",
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.size = SZ_16M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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},
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};
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const struct spi_nor_manufacturer spi_nor_gigadevice = {
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.name = "gigadevice",
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.parts = gigadevice_nor_parts,
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.nparts = ARRAY_SIZE(gigadevice_nor_parts),
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};
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