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334955ef96
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/20110601180610.054254048@duck.linux-mips.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de> arch/arm/mach-footbridge/isa-timer.c | 2 +- arch/mips/cobalt/time.c | 2 +- arch/mips/jazz/irq.c | 2 +- arch/mips/kernel/i8253.c | 2 +- arch/mips/mti-malta/malta-time.c | 2 +- arch/mips/sgi-ip22/ip22-time.c | 2 +- arch/mips/sni/time.c | 2 +- arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apm_32.c | 2 +- arch/x86/kernel/hpet.c | 2 +- arch/x86/kernel/i8253.c | 2 +- arch/x86/kernel/time.c | 2 +- drivers/block/hd.c | 2 +- drivers/clocksource/i8253.c | 2 +- drivers/input/gameport/gameport.c | 2 +- drivers/input/joystick/analog.c | 2 +- drivers/input/misc/pcspkr.c | 2 +- include/linux/i8253.h | 11 +++++++++++ sound/drivers/pcsp/pcsp.h | 2 +- 19 files changed, 29 insertions(+), 18 deletions(-)
165 lines
4.0 KiB
C
165 lines
4.0 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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#include <linux/i8253.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <asm/cpu.h>
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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#include <asm/msc01_ic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/prom.h>
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#include <asm/mips-boards/maltaint.h>
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unsigned long cpu_khz;
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static int mips_cpu_timer_irq;
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static int mips_cpu_perf_irq;
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extern int cp0_perfcount_irq;
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static void mips_timer_dispatch(void)
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{
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do_IRQ(mips_cpu_timer_irq);
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}
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static void mips_perf_dispatch(void)
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{
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do_IRQ(mips_cpu_perf_irq);
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}
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/*
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* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
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*/
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static unsigned int __init estimate_cpu_frequency(void)
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{
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unsigned int prid = read_c0_prid() & 0xffff00;
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unsigned int count;
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unsigned long flags;
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unsigned int start;
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local_irq_save(flags);
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/* Start counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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/* Start r4k counter. */
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start = read_c0_count();
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/* Read counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count() - start;
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/* restore interrupts */
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local_irq_restore(flags);
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mips_hpt_frequency = count;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count *= 2;
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count += 5000; /* round */
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count -= count%10000;
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return count;
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}
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void read_persistent_clock(struct timespec *ts)
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{
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ts->tv_sec = mc146818_get_cmos_time();
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ts->tv_nsec = 0;
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}
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static void __init plat_perf_setup(void)
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{
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
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mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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} else
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#endif
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if (cp0_perfcount_irq >= 0) {
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if (cpu_has_vint)
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set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
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mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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#ifdef CONFIG_SMP
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irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
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#endif
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}
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}
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unsigned int __cpuinit get_c0_compare_int(void)
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{
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
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mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
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} else
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#endif
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{
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if (cpu_has_vint)
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set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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return mips_cpu_timer_irq;
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}
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void __init plat_time_init(void)
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{
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unsigned int est_freq;
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/* Set Data mode - binary. */
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CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
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est_freq = estimate_cpu_frequency();
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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(est_freq%1000000)*100/1000000);
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cpu_khz = est_freq / 1000;
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mips_scroll_message();
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#ifdef CONFIG_I8253 /* Only Malta has a PIT */
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setup_pit_timer();
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#endif
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plat_perf_setup();
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}
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