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c23bfc3835
Most PCI implementations perform simple root bus scanning. Rather than having each group of platforms provide a duplicated bus scan function, provide the PCI configuration ops structure via the hw_pci structure, and call the root bus scanning function from core ARM PCI code. Acked-by: Krzysztof Hałasa <khc@pm.waw.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* linux/arch/arm/mach-integrator/pci-integrator.c
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* PCI functions for Integrator
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <mach/irqs.h>
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/*
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* A small note about bridges and interrupts. The DECchip 21050 (and
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* later) adheres to the PCI-PCI bridge specification. This says that
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* the interrupts on the other side of a bridge are swizzled in the
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* following manner:
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*
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* Dev Interrupt Interrupt
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* Pin on Pin on
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* Device Connector
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*
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* 4 A A
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* B B
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* C C
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* D D
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*
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* 5 A B
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* B C
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* C D
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* D A
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*
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* 6 A C
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* B D
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* C A
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* D B
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*
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* 7 A D
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* B A
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* C B
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* D C
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*
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* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
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* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
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*/
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/*
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* This routine handles multiple bridges.
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*/
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static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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if (*pinp == 0)
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*pinp = 1;
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return pci_common_swizzle(dev, pinp);
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}
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static int irq_tab[4] __initdata = {
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IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
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};
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/*
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* map the specified device/slot/pin to an IRQ. This works out such
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* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
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*/
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static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int intnr = ((slot - 9) + (pin - 1)) & 3;
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return irq_tab[intnr];
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}
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extern void pci_v3_init(void *);
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static struct hw_pci integrator_pci __initdata = {
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.swizzle = integrator_swizzle,
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.map_irq = integrator_map_irq,
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.setup = pci_v3_setup,
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.nr_controllers = 1,
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.ops = &pci_v3_ops,
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.preinit = pci_v3_preinit,
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.postinit = pci_v3_postinit,
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};
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static int __init integrator_pci_init(void)
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{
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if (machine_is_integrator())
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pci_common_init(&integrator_pci);
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return 0;
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}
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subsys_initcall(integrator_pci_init);
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