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59078d4b96
Kill the "mm->context.ia32_compat" check in handle_riprel_insn(), if it is true insn_rip_relative() must return false. validate_insn_bits() passed "ia32_compat" as !x86_64 to insn_init(), and insn_rip_relative() checks insn->x86_64. Also, remove the no longer needed "struct mm_struct *mm" argument and the unnecessary "return" at the end. Signed-off-by: Oleg Nesterov <oleg@redhat.com> Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Reviewed-by: Jim Keniston <jkenisto@us.ibm.com> Acked-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
709 lines
22 KiB
C
709 lines
22 KiB
C
/*
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* User-space Probes (UProbes) for x86
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2008-2011
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* Authors:
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* Srikar Dronamraju
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* Jim Keniston
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/uprobes.h>
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#include <linux/uaccess.h>
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#include <linux/kdebug.h>
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#include <asm/processor.h>
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#include <asm/insn.h>
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/* Post-execution fixups. */
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/* No fixup needed */
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#define UPROBE_FIX_NONE 0x0
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/* Adjust IP back to vicinity of actual insn */
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#define UPROBE_FIX_IP 0x1
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/* Adjust the return address of a call insn */
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#define UPROBE_FIX_CALL 0x2
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/* Instruction will modify TF, don't change it */
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#define UPROBE_FIX_SETF 0x4
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#define UPROBE_FIX_RIP_AX 0x8000
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#define UPROBE_FIX_RIP_CX 0x4000
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#define UPROBE_TRAP_NR UINT_MAX
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/* Adaptations for mhiramat x86 decoder v14. */
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#define OPCODE1(insn) ((insn)->opcode.bytes[0])
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#define OPCODE2(insn) ((insn)->opcode.bytes[1])
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#define OPCODE3(insn) ((insn)->opcode.bytes[2])
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#define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
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#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
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(((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
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(b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
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(b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
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(bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
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<< (row % 32))
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/*
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* Good-instruction tables for 32-bit apps. This is non-const and volatile
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* to keep gcc from statically optimizing it out, as variable_test_bit makes
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* some versions of gcc to think only *(unsigned long*) is used.
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*/
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static volatile u32 good_insns_32[256 / 32] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ---------------------------------------------- */
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W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */
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W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
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W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */
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W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */
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W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
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W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
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W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
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W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
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W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
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W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
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W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
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W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
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W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
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W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
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W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
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W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
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/* ---------------------------------------------- */
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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/* Using this for both 64-bit and 32-bit apps */
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static volatile u32 good_2byte_insns[256 / 32] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ---------------------------------------------- */
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W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */
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W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
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W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
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W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */
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W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
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W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
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W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
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W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */
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W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
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W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
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W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
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W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
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W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
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W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
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W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
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W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */
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/* ---------------------------------------------- */
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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#ifdef CONFIG_X86_64
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/* Good-instruction tables for 64-bit apps */
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static volatile u32 good_insns_64[256 / 32] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ---------------------------------------------- */
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W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */
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W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
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W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */
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W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */
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W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */
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W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
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W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
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W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
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W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
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W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
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W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
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W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
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W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
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W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
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W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
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W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
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/* ---------------------------------------------- */
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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#endif
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#undef W
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/*
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* opcodes we'll probably never support:
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*
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* 6c-6d, e4-e5, ec-ed - in
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* 6e-6f, e6-e7, ee-ef - out
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* cc, cd - int3, int
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* cf - iret
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* d6 - illegal instruction
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* f1 - int1/icebp
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* f4 - hlt
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* fa, fb - cli, sti
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* 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2
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*
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* invalid opcodes in 64-bit mode:
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*
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* 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5
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* 63 - we support this opcode in x86_64 but not in i386.
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*
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* opcodes we may need to refine support for:
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*
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* 0f - 2-byte instructions: For many of these instructions, the validity
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* depends on the prefix and/or the reg field. On such instructions, we
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* just consider the opcode combination valid if it corresponds to any
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* valid instruction.
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*
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* 8f - Group 1 - only reg = 0 is OK
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* c6-c7 - Group 11 - only reg = 0 is OK
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* d9-df - fpu insns with some illegal encodings
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* f2, f3 - repnz, repz prefixes. These are also the first byte for
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* certain floating-point instructions, such as addsd.
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*
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* fe - Group 4 - only reg = 0 or 1 is OK
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* ff - Group 5 - only reg = 0-6 is OK
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*
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* others -- Do we need to support these?
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*
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* 0f - (floating-point?) prefetch instructions
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* 07, 17, 1f - pop es, pop ss, pop ds
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* 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
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* but 64 and 65 (fs: and gs:) seem to be used, so we support them
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* 67 - addr16 prefix
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* ce - into
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* f0 - lock prefix
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*/
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/*
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* TODO:
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* - Where necessary, examine the modrm byte and allow only valid instructions
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* in the different Groups and fpu instructions.
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*/
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static bool is_prefix_bad(struct insn *insn)
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{
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int i;
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for (i = 0; i < insn->prefixes.nbytes; i++) {
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switch (insn->prefixes.bytes[i]) {
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case 0x26: /* INAT_PFX_ES */
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case 0x2E: /* INAT_PFX_CS */
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case 0x36: /* INAT_PFX_DS */
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case 0x3E: /* INAT_PFX_SS */
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case 0xF0: /* INAT_PFX_LOCK */
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return true;
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}
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}
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return false;
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}
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static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn)
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{
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insn_init(insn, auprobe->insn, false);
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/* Skip good instruction prefixes; reject "bad" ones. */
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insn_get_opcode(insn);
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if (is_prefix_bad(insn))
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return -ENOTSUPP;
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if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_32))
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return 0;
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if (insn->opcode.nbytes == 2) {
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if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
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return 0;
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}
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return -ENOTSUPP;
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}
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#ifdef CONFIG_X86_64
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/*
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* If arch_uprobe->insn doesn't use rip-relative addressing, return
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* immediately. Otherwise, rewrite the instruction so that it accesses
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* its memory operand indirectly through a scratch register. Set
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* arch_uprobe->fixups and arch_uprobe->rip_rela_target_address
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* accordingly. (The contents of the scratch register will be saved
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* before we single-step the modified instruction, and restored
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* afterward.)
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*
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* We do this because a rip-relative instruction can access only a
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* relatively small area (+/- 2 GB from the instruction), and the XOL
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* area typically lies beyond that area. At least for instructions
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* that store to memory, we can't execute the original instruction
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* and "fix things up" later, because the misdirected store could be
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* disastrous.
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*
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* Some useful facts about rip-relative instructions:
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*
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* - There's always a modrm byte.
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* - There's never a SIB byte.
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* - The displacement is always 4 bytes.
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*/
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static void
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handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn)
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{
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u8 *cursor;
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u8 reg;
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if (!insn_rip_relative(insn))
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return;
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/*
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* insn_rip_relative() would have decoded rex_prefix, modrm.
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* Clear REX.b bit (extension of MODRM.rm field):
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* we want to encode rax/rcx, not r8/r9.
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*/
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if (insn->rex_prefix.nbytes) {
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cursor = auprobe->insn + insn_offset_rex_prefix(insn);
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*cursor &= 0xfe; /* Clearing REX.B bit */
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}
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/*
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* Point cursor at the modrm byte. The next 4 bytes are the
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* displacement. Beyond the displacement, for some instructions,
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* is the immediate operand.
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*/
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cursor = auprobe->insn + insn_offset_modrm(insn);
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insn_get_length(insn);
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/*
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* Convert from rip-relative addressing to indirect addressing
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* via a scratch register. Change the r/m field from 0x5 (%rip)
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* to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field.
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*/
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reg = MODRM_REG(insn);
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if (reg == 0) {
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/*
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* The register operand (if any) is either the A register
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* (%rax, %eax, etc.) or (if the 0x4 bit is set in the
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* REX prefix) %r8. In any case, we know the C register
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* is NOT the register operand, so we use %rcx (register
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* #1) for the scratch register.
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*/
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auprobe->fixups = UPROBE_FIX_RIP_CX;
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/* Change modrm from 00 000 101 to 00 000 001. */
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*cursor = 0x1;
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} else {
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/* Use %rax (register #0) for the scratch register. */
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auprobe->fixups = UPROBE_FIX_RIP_AX;
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/* Change modrm from 00 xxx 101 to 00 xxx 000 */
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*cursor = (reg << 3);
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}
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/* Target address = address of next instruction + (signed) offset */
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auprobe->rip_rela_target_address = (long)insn->length + insn->displacement.value;
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/* Displacement field is gone; slide immediate field (if any) over. */
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if (insn->immediate.nbytes) {
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cursor++;
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memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes);
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}
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}
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static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn)
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{
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insn_init(insn, auprobe->insn, true);
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/* Skip good instruction prefixes; reject "bad" ones. */
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insn_get_opcode(insn);
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if (is_prefix_bad(insn))
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return -ENOTSUPP;
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if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_64))
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return 0;
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if (insn->opcode.nbytes == 2) {
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if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
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return 0;
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}
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return -ENOTSUPP;
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}
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static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
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{
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if (mm->context.ia32_compat)
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return validate_insn_32bits(auprobe, insn);
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return validate_insn_64bits(auprobe, insn);
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}
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#else /* 32-bit: */
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static void handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn)
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{
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/* No RIP-relative addressing on 32-bit */
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}
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static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
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{
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return validate_insn_32bits(auprobe, insn);
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}
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#endif /* CONFIG_X86_64 */
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/**
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* arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
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* @mm: the probed address space.
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* @arch_uprobe: the probepoint information.
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* @addr: virtual address at which to install the probepoint
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* Return 0 on success or a -ve number on error.
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*/
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int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
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{
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struct insn insn;
|
|
bool fix_ip = true, fix_call = false;
|
|
int ret;
|
|
|
|
ret = validate_insn_bits(auprobe, mm, &insn);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Figure out which fixups arch_uprobe_post_xol() will need to perform,
|
|
* and annotate arch_uprobe->fixups accordingly. To start with, ->fixups
|
|
* is either zero or it reflects rip-related fixups.
|
|
*/
|
|
handle_riprel_insn(auprobe, &insn);
|
|
|
|
switch (OPCODE1(&insn)) {
|
|
case 0x9d: /* popf */
|
|
auprobe->fixups |= UPROBE_FIX_SETF;
|
|
break;
|
|
case 0xc3: /* ret or lret -- ip is correct */
|
|
case 0xcb:
|
|
case 0xc2:
|
|
case 0xca:
|
|
fix_ip = false;
|
|
break;
|
|
case 0xe8: /* call relative - Fix return addr */
|
|
fix_call = true;
|
|
break;
|
|
case 0x9a: /* call absolute - Fix return addr, not ip */
|
|
fix_call = true;
|
|
fix_ip = false;
|
|
break;
|
|
case 0xea: /* jmp absolute -- ip is correct */
|
|
fix_ip = false;
|
|
break;
|
|
case 0xff:
|
|
insn_get_modrm(&insn);
|
|
switch (MODRM_REG(&insn)) {
|
|
case 2: case 3: /* call or lcall, indirect */
|
|
fix_call = true;
|
|
case 4: case 5: /* jmp or ljmp, indirect */
|
|
fix_ip = false;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (fix_ip)
|
|
auprobe->fixups |= UPROBE_FIX_IP;
|
|
if (fix_call)
|
|
auprobe->fixups |= UPROBE_FIX_CALL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
/*
|
|
* If we're emulating a rip-relative instruction, save the contents
|
|
* of the scratch register and store the target address in that register.
|
|
*/
|
|
static void
|
|
pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs,
|
|
struct arch_uprobe_task *autask)
|
|
{
|
|
if (auprobe->fixups & UPROBE_FIX_RIP_AX) {
|
|
autask->saved_scratch_register = regs->ax;
|
|
regs->ax = current->utask->vaddr;
|
|
regs->ax += auprobe->rip_rela_target_address;
|
|
} else if (auprobe->fixups & UPROBE_FIX_RIP_CX) {
|
|
autask->saved_scratch_register = regs->cx;
|
|
regs->cx = current->utask->vaddr;
|
|
regs->cx += auprobe->rip_rela_target_address;
|
|
}
|
|
}
|
|
#else
|
|
static void
|
|
pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs,
|
|
struct arch_uprobe_task *autask)
|
|
{
|
|
/* No RIP-relative addressing on 32-bit */
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* arch_uprobe_pre_xol - prepare to execute out of line.
|
|
* @auprobe: the probepoint information.
|
|
* @regs: reflects the saved user state of current task.
|
|
*/
|
|
int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|
{
|
|
struct arch_uprobe_task *autask;
|
|
|
|
autask = ¤t->utask->autask;
|
|
autask->saved_trap_nr = current->thread.trap_nr;
|
|
current->thread.trap_nr = UPROBE_TRAP_NR;
|
|
regs->ip = current->utask->xol_vaddr;
|
|
pre_xol_rip_insn(auprobe, regs, autask);
|
|
|
|
autask->saved_tf = !!(regs->flags & X86_EFLAGS_TF);
|
|
regs->flags |= X86_EFLAGS_TF;
|
|
if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
|
|
set_task_blockstep(current, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This function is called by arch_uprobe_post_xol() to adjust the return
|
|
* address pushed by a call instruction executed out of line.
|
|
*/
|
|
static int adjust_ret_addr(unsigned long sp, long correction)
|
|
{
|
|
int rasize, ncopied;
|
|
long ra = 0;
|
|
|
|
if (is_ia32_task())
|
|
rasize = 4;
|
|
else
|
|
rasize = 8;
|
|
|
|
ncopied = copy_from_user(&ra, (void __user *)sp, rasize);
|
|
if (unlikely(ncopied))
|
|
return -EFAULT;
|
|
|
|
ra += correction;
|
|
ncopied = copy_to_user((void __user *)sp, &ra, rasize);
|
|
if (unlikely(ncopied))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
static bool is_riprel_insn(struct arch_uprobe *auprobe)
|
|
{
|
|
return ((auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) != 0);
|
|
}
|
|
|
|
static void
|
|
handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction)
|
|
{
|
|
if (is_riprel_insn(auprobe)) {
|
|
struct arch_uprobe_task *autask;
|
|
|
|
autask = ¤t->utask->autask;
|
|
if (auprobe->fixups & UPROBE_FIX_RIP_AX)
|
|
regs->ax = autask->saved_scratch_register;
|
|
else
|
|
regs->cx = autask->saved_scratch_register;
|
|
|
|
/*
|
|
* The original instruction includes a displacement, and so
|
|
* is 4 bytes longer than what we've just single-stepped.
|
|
* Fall through to handle stuff like "jmpq *...(%rip)" and
|
|
* "callq *...(%rip)".
|
|
*/
|
|
if (correction)
|
|
*correction += 4;
|
|
}
|
|
}
|
|
#else
|
|
static void
|
|
handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction)
|
|
{
|
|
/* No RIP-relative addressing on 32-bit */
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* If xol insn itself traps and generates a signal(Say,
|
|
* SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
|
|
* instruction jumps back to its own address. It is assumed that anything
|
|
* like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
|
|
*
|
|
* arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
|
|
* arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
|
|
* UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
|
|
*/
|
|
bool arch_uprobe_xol_was_trapped(struct task_struct *t)
|
|
{
|
|
if (t->thread.trap_nr != UPROBE_TRAP_NR)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* Called after single-stepping. To avoid the SMP problems that can
|
|
* occur when we temporarily put back the original opcode to
|
|
* single-step, we single-stepped a copy of the instruction.
|
|
*
|
|
* This function prepares to resume execution after the single-step.
|
|
* We have to fix things up as follows:
|
|
*
|
|
* Typically, the new ip is relative to the copied instruction. We need
|
|
* to make it relative to the original instruction (FIX_IP). Exceptions
|
|
* are return instructions and absolute or indirect jump or call instructions.
|
|
*
|
|
* If the single-stepped instruction was a call, the return address that
|
|
* is atop the stack is the address following the copied instruction. We
|
|
* need to make it the address following the original instruction (FIX_CALL).
|
|
*
|
|
* If the original instruction was a rip-relative instruction such as
|
|
* "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
|
|
* instruction using a scratch register -- e.g., "movl %edx,(%rax)".
|
|
* We need to restore the contents of the scratch register and adjust
|
|
* the ip, keeping in mind that the instruction we executed is 4 bytes
|
|
* shorter than the original instruction (since we squeezed out the offset
|
|
* field). (FIX_RIP_AX or FIX_RIP_CX)
|
|
*/
|
|
int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|
{
|
|
struct uprobe_task *utask;
|
|
long correction;
|
|
int result = 0;
|
|
|
|
WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
|
|
|
|
utask = current->utask;
|
|
current->thread.trap_nr = utask->autask.saved_trap_nr;
|
|
correction = (long)(utask->vaddr - utask->xol_vaddr);
|
|
handle_riprel_post_xol(auprobe, regs, &correction);
|
|
if (auprobe->fixups & UPROBE_FIX_IP)
|
|
regs->ip += correction;
|
|
|
|
if (auprobe->fixups & UPROBE_FIX_CALL)
|
|
result = adjust_ret_addr(regs->sp, correction);
|
|
|
|
/*
|
|
* arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
|
|
* so we can get an extra SIGTRAP if we do not clear TF. We need
|
|
* to examine the opcode to make it right.
|
|
*/
|
|
if (utask->autask.saved_tf)
|
|
send_sig(SIGTRAP, current, 0);
|
|
else if (!(auprobe->fixups & UPROBE_FIX_SETF))
|
|
regs->flags &= ~X86_EFLAGS_TF;
|
|
|
|
return result;
|
|
}
|
|
|
|
/* callback routine for handling exceptions. */
|
|
int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
|
|
{
|
|
struct die_args *args = data;
|
|
struct pt_regs *regs = args->regs;
|
|
int ret = NOTIFY_DONE;
|
|
|
|
/* We are only interested in userspace traps */
|
|
if (regs && !user_mode_vm(regs))
|
|
return NOTIFY_DONE;
|
|
|
|
switch (val) {
|
|
case DIE_INT3:
|
|
if (uprobe_pre_sstep_notifier(regs))
|
|
ret = NOTIFY_STOP;
|
|
|
|
break;
|
|
|
|
case DIE_DEBUG:
|
|
if (uprobe_post_sstep_notifier(regs))
|
|
ret = NOTIFY_STOP;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* This function gets called when XOL instruction either gets trapped or
|
|
* the thread has a fatal signal, so reset the instruction pointer to its
|
|
* probed address.
|
|
*/
|
|
void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|
{
|
|
struct uprobe_task *utask = current->utask;
|
|
|
|
current->thread.trap_nr = utask->autask.saved_trap_nr;
|
|
handle_riprel_post_xol(auprobe, regs, NULL);
|
|
instruction_pointer_set(regs, utask->vaddr);
|
|
|
|
/* clear TF if it was set by us in arch_uprobe_pre_xol() */
|
|
if (!utask->autask.saved_tf)
|
|
regs->flags &= ~X86_EFLAGS_TF;
|
|
}
|
|
|
|
/*
|
|
* Skip these instructions as per the currently known x86 ISA.
|
|
* rep=0x66*; nop=0x90
|
|
*/
|
|
static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_UINSN_BYTES; i++) {
|
|
if (auprobe->insn[i] == 0x66)
|
|
continue;
|
|
|
|
if (auprobe->insn[i] == 0x90) {
|
|
regs->ip += i + 1;
|
|
return true;
|
|
}
|
|
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|
{
|
|
bool ret = __skip_sstep(auprobe, regs);
|
|
if (ret && (regs->flags & X86_EFLAGS_TF))
|
|
send_sig(SIGTRAP, current, 0);
|
|
return ret;
|
|
}
|
|
|
|
unsigned long
|
|
arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
|
|
{
|
|
int rasize, ncopied;
|
|
unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
|
|
|
|
rasize = is_ia32_task() ? 4 : 8;
|
|
ncopied = copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize);
|
|
if (unlikely(ncopied))
|
|
return -1;
|
|
|
|
/* check whether address has been already hijacked */
|
|
if (orig_ret_vaddr == trampoline_vaddr)
|
|
return orig_ret_vaddr;
|
|
|
|
ncopied = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
|
|
if (likely(!ncopied))
|
|
return orig_ret_vaddr;
|
|
|
|
if (ncopied != rasize) {
|
|
pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
|
|
"%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
|
|
|
|
force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
|
|
}
|
|
|
|
return -1;
|
|
}
|