Michael Tretter 58ee6baf39 soc: xilinx: vcu: make the PLL configurable ... Do not configure the PLL when probing the driver, but register the clock in the clock framework and do the configuration based on the respective callbacks. This is necessary to allow the consumers, i.e., encoder and decoder drivers, of the xlnx_vcu clock provider to set the clock rate and actually enable the clocks without relying on some pre-configuration. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-11-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-02-08 18:31:25 -08:00
..
Kconfig	soc: xilinx: vcu: register PLL as fixed rate clock	2021-02-08 18:31:25 -08:00
Makefile	drivers: soc: xilinx: Add ZynqMP power domain driver	2019-02-12 13:38:16 +01:00
xlnx_vcu.c	soc: xilinx: vcu: make the PLL configurable	2021-02-08 18:31:25 -08:00
zynqmp_pm_domains.c	firmware: xilinx: Remove eemi ops for set_requirement	2020-04-28 15:45:09 +02:00
zynqmp_power.c	soc: xilinx: Fix error code in zynqmp_pm_probe()	2020-06-18 10:07:17 +02:00