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Some of the PHY and MDIO drivers refer to the COPYING file in the main directory of this archive. This is the main license for Linux, thus GPLv2 plus syscall extension. Fixup the MODULE_LICENSE() where needed and add an SDPX header for GPLv2. Cc: David Daney <david.daney@cavium.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
222 lines
4.9 KiB
C
222 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2011 - 2012 Cavium, Inc.
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#define PHY_ID_BCM8706 0x0143bdc1
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#define PHY_ID_BCM8727 0x0143bff0
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#define BCM87XX_PMD_RX_SIGNAL_DETECT (MII_ADDR_C45 | 0x1000a)
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#define BCM87XX_10GBASER_PCS_STATUS (MII_ADDR_C45 | 0x30020)
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#define BCM87XX_XGXS_LANE_STATUS (MII_ADDR_C45 | 0x40018)
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#define BCM87XX_LASI_CONTROL (MII_ADDR_C45 | 0x39002)
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#define BCM87XX_LASI_STATUS (MII_ADDR_C45 | 0x39005)
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#if IS_ENABLED(CONFIG_OF_MDIO)
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/* Set and/or override some configuration registers based on the
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* broadcom,c45-reg-init property stored in the of_node for the phydev.
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*
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* broadcom,c45-reg-init = <devid reg mask value>,...;
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*
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* There may be one or more sets of <devid reg mask value>:
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*
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* devid: which sub-device to use.
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* reg: the register.
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* mask: if non-zero, ANDed with existing register value.
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* value: ORed with the masked value and written to the regiser.
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*
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*/
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static int bcm87xx_of_reg_init(struct phy_device *phydev)
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{
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const __be32 *paddr;
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const __be32 *paddr_end;
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int len, ret;
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if (!phydev->mdio.dev.of_node)
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return 0;
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paddr = of_get_property(phydev->mdio.dev.of_node,
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"broadcom,c45-reg-init", &len);
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if (!paddr)
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return 0;
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paddr_end = paddr + (len /= sizeof(*paddr));
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ret = 0;
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while (paddr + 3 < paddr_end) {
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u16 devid = be32_to_cpup(paddr++);
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u16 reg = be32_to_cpup(paddr++);
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u16 mask = be32_to_cpup(paddr++);
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u16 val_bits = be32_to_cpup(paddr++);
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int val;
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u32 regnum = MII_ADDR_C45 | (devid << 16) | reg;
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val = 0;
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if (mask) {
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val = phy_read(phydev, regnum);
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if (val < 0) {
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ret = val;
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goto err;
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}
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val &= mask;
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}
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val |= val_bits;
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ret = phy_write(phydev, regnum, val);
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if (ret < 0)
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goto err;
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}
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err:
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return ret;
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}
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#else
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static int bcm87xx_of_reg_init(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int bcm87xx_config_init(struct phy_device *phydev)
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{
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linkmode_zero(phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
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phydev->supported);
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linkmode_zero(phydev->advertising);
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linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
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phydev->advertising);
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phydev->state = PHY_NOLINK;
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phydev->autoneg = AUTONEG_DISABLE;
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bcm87xx_of_reg_init(phydev);
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return 0;
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}
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static int bcm87xx_config_aneg(struct phy_device *phydev)
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{
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return -EINVAL;
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}
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static int bcm87xx_read_status(struct phy_device *phydev)
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{
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int rx_signal_detect;
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int pcs_status;
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int xgxs_lane_status;
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rx_signal_detect = phy_read(phydev, BCM87XX_PMD_RX_SIGNAL_DETECT);
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if (rx_signal_detect < 0)
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return rx_signal_detect;
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if ((rx_signal_detect & 1) == 0)
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goto no_link;
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pcs_status = phy_read(phydev, BCM87XX_10GBASER_PCS_STATUS);
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if (pcs_status < 0)
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return pcs_status;
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if ((pcs_status & 1) == 0)
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goto no_link;
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xgxs_lane_status = phy_read(phydev, BCM87XX_XGXS_LANE_STATUS);
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if (xgxs_lane_status < 0)
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return xgxs_lane_status;
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if ((xgxs_lane_status & 0x1000) == 0)
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goto no_link;
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phydev->speed = 10000;
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phydev->link = 1;
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phydev->duplex = 1;
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return 0;
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no_link:
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phydev->link = 0;
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return 0;
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}
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static int bcm87xx_config_intr(struct phy_device *phydev)
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{
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int reg, err;
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reg = phy_read(phydev, BCM87XX_LASI_CONTROL);
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if (reg < 0)
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return reg;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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reg |= 1;
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else
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reg &= ~1;
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err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg);
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return err;
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}
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static int bcm87xx_did_interrupt(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read(phydev, BCM87XX_LASI_STATUS);
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if (reg < 0) {
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phydev_err(phydev,
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"Error: Read of BCM87XX_LASI_STATUS failed: %d\n",
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reg);
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return 0;
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}
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return (reg & 1) != 0;
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}
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static int bcm87xx_ack_interrupt(struct phy_device *phydev)
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{
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/* Reading the LASI status clears it. */
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bcm87xx_did_interrupt(phydev);
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return 0;
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}
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static int bcm8706_match_phy_device(struct phy_device *phydev)
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{
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return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;
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}
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static int bcm8727_match_phy_device(struct phy_device *phydev)
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{
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return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;
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}
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static struct phy_driver bcm87xx_driver[] = {
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{
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.phy_id = PHY_ID_BCM8706,
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.phy_id_mask = 0xffffffff,
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.name = "Broadcom BCM8706",
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.features = PHY_10GBIT_FEC_FEATURES,
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.config_init = bcm87xx_config_init,
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.config_aneg = bcm87xx_config_aneg,
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.read_status = bcm87xx_read_status,
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.ack_interrupt = bcm87xx_ack_interrupt,
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.config_intr = bcm87xx_config_intr,
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.did_interrupt = bcm87xx_did_interrupt,
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.match_phy_device = bcm8706_match_phy_device,
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}, {
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.phy_id = PHY_ID_BCM8727,
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.phy_id_mask = 0xffffffff,
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.name = "Broadcom BCM8727",
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.features = PHY_10GBIT_FEC_FEATURES,
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.config_init = bcm87xx_config_init,
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.config_aneg = bcm87xx_config_aneg,
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.read_status = bcm87xx_read_status,
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.ack_interrupt = bcm87xx_ack_interrupt,
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.config_intr = bcm87xx_config_intr,
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.did_interrupt = bcm87xx_did_interrupt,
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.match_phy_device = bcm8727_match_phy_device,
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} };
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module_phy_driver(bcm87xx_driver);
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MODULE_LICENSE("GPL v2");
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