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25732ad493
1) workaround a h/w reset issue 2) to improve the determination of FPGA-based h/w in the arch/ia64/sn/kernel/tiocx code. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
51 lines
2.2 KiB
C
51 lines
2.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#ifndef _ASM_IA64_SN_L1_H
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#define _ASM_IA64_SN_L1_H
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/* brick type response codes */
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#define L1_BRICKTYPE_PX 0x23 /* # */
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#define L1_BRICKTYPE_PE 0x25 /* % */
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#define L1_BRICKTYPE_N_p0 0x26 /* & */
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#define L1_BRICKTYPE_IP45 0x34 /* 4 */
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#define L1_BRICKTYPE_IP41 0x35 /* 5 */
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#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */
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#define L1_BRICKTYPE_IX 0x3d /* = */
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#define L1_BRICKTYPE_IP34 0x61 /* a */
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#define L1_BRICKTYPE_GA 0x62 /* b */
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#define L1_BRICKTYPE_C 0x63 /* c */
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#define L1_BRICKTYPE_OPUS_TIO 0x66 /* f */
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#define L1_BRICKTYPE_I 0x69 /* i */
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#define L1_BRICKTYPE_N 0x6e /* n */
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#define L1_BRICKTYPE_OPUS 0x6f /* o */
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#define L1_BRICKTYPE_P 0x70 /* p */
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#define L1_BRICKTYPE_R 0x72 /* r */
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#define L1_BRICKTYPE_CHI_CG 0x76 /* v */
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#define L1_BRICKTYPE_X 0x78 /* x */
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#define L1_BRICKTYPE_X2 0x79 /* y */
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#define L1_BRICKTYPE_SA 0x5e /* ^ */
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#define L1_BRICKTYPE_PA 0x6a /* j */
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#define L1_BRICKTYPE_IA 0x6b /* k */
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#define L1_BRICKTYPE_ATHENA 0x2b /* + */
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#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
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/* board type response codes */
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#define L1_BOARDTYPE_IP69 0x0100 /* CA */
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#define L1_BOARDTYPE_IP63 0x0200 /* CB */
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#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
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#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
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#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
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#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
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#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
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#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
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#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
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#endif /* _ASM_IA64_SN_L1_H */
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