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06c67befee
Newer ARMs have a 40 bit physical address space, but mapping physical
memory above 4G needs a special page table format which we (currently?) do
not use for userspace mappings, so what happens instead is that mapping an
address >= 4G will happily discard the upper bits and wrap.
There is a valid_mmap_phys_addr_range() arch hook where we could check for
>= 4G addresses and deny the mapping, but this hook takes an unsigned long
address:
static inline int valid_mmap_phys_addr_range(unsigned long addr, size_t size);
And drivers/char/mem.c:mmap_mem() calls it like this:
static int mmap_mem(struct file * file, struct vm_area_struct * vma)
{
size_t size = vma->vm_end - vma->vm_start;
if (!valid_mmap_phys_addr_range(vma->vm_pgoff << PAGE_SHIFT, size))
So that's not much help either.
This patch makes the hook take a pfn instead of a phys address.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
473 lines
13 KiB
C
473 lines
13 KiB
C
#ifndef _ASM_IA64_IO_H
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#define _ASM_IA64_IO_H
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/*
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* This file contains the definitions for the emulated IO instructions
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* inb/inw/inl/outb/outw/outl and the "string versions" of the same
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* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
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* versions of the single-IO instructions (inb_p/inw_p/..).
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*
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* This file is not meant to be obfuscating: it's just complicated to
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* (a) handle it all in a way that makes gcc able to optimize it as
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* well as possible and (b) trying to avoid writing the same thing
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* over and over again with slight variations and possibly making a
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* mistake somewhere.
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*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
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* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
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*/
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/* We don't use IO slowdowns on the ia64, but.. */
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#define __SLOW_DOWN_IO do { } while (0)
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#define SLOW_DOWN_IO do { } while (0)
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#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
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/*
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* The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
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* large machines may have multiple other I/O spaces so we can't place any a priori limit
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* on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
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*/
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#define IO_SPACE_LIMIT 0xffffffffffffffffUL
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#define MAX_IO_SPACES_BITS 4
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#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
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#define IO_SPACE_BITS 24
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#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
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#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
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#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
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#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
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#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
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struct io_space {
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unsigned long mmio_base; /* base in MMIO space */
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int sparse;
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};
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extern struct io_space io_space[];
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extern unsigned int num_io_spaces;
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# ifdef __KERNEL__
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/*
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* All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
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* 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
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* 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
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*
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* ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
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* code that uses bare port numbers without the prerequisite pci_iomap().
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*/
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#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
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#define PIO_MASK (PIO_OFFSET - 1)
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#define PIO_RESERVED __IA64_UNCACHED_OFFSET
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#define HAVE_ARCH_PIO_SIZE
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#include <asm/intrinsics.h>
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#include <asm/machvec.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm-generic/iomap.h>
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/*
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* Change virtual addresses to physical addresses and vv.
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*/
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static inline unsigned long
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virt_to_phys (volatile void *address)
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{
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return (unsigned long) address - PAGE_OFFSET;
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}
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static inline void*
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phys_to_virt (unsigned long address)
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{
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return (void *) (address + PAGE_OFFSET);
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}
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
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extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
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extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
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/*
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* The following two macros are deprecated and scheduled for removal.
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* Please use the PCI-DMA interface defined in <asm/pci.h> instead.
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*/
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#define bus_to_virt phys_to_virt
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#define virt_to_bus virt_to_phys
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#define page_to_bus page_to_phys
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# endif /* KERNEL */
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/*
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* Memory fence w/accept. This should never be used in code that is
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* not IA-64 specific.
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*/
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#define __ia64_mf_a() ia64_mfa()
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/**
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* ___ia64_mmiowb - I/O write barrier
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*
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* Ensure ordering of I/O space writes. This will make sure that writes
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* following the barrier will arrive after all previous writes. For most
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* ia64 platforms, this is a simple 'mf.a' instruction.
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*
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* See Documentation/DocBook/deviceiobook.tmpl for more information.
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*/
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static inline void ___ia64_mmiowb(void)
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{
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ia64_mfa();
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}
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static inline void*
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__ia64_mk_io_addr (unsigned long port)
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{
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struct io_space *space;
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unsigned long offset;
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space = &io_space[IO_SPACE_NR(port)];
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port = IO_SPACE_PORT(port);
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if (space->sparse)
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offset = IO_SPACE_SPARSE_ENCODING(port);
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else
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offset = port;
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return (void *) (space->mmio_base | offset);
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}
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#define __ia64_inb ___ia64_inb
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#define __ia64_inw ___ia64_inw
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#define __ia64_inl ___ia64_inl
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#define __ia64_outb ___ia64_outb
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#define __ia64_outw ___ia64_outw
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#define __ia64_outl ___ia64_outl
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#define __ia64_readb ___ia64_readb
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#define __ia64_readw ___ia64_readw
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#define __ia64_readl ___ia64_readl
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#define __ia64_readq ___ia64_readq
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#define __ia64_readb_relaxed ___ia64_readb
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#define __ia64_readw_relaxed ___ia64_readw
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#define __ia64_readl_relaxed ___ia64_readl
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#define __ia64_readq_relaxed ___ia64_readq
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#define __ia64_writeb ___ia64_writeb
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#define __ia64_writew ___ia64_writew
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#define __ia64_writel ___ia64_writel
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#define __ia64_writeq ___ia64_writeq
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#define __ia64_mmiowb ___ia64_mmiowb
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/*
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* For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
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* that the access has completed before executing other I/O accesses. Since we're doing
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* the accesses through an uncachable (UC) translation, the CPU will execute them in
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* program order. However, we still need to tell the compiler not to shuffle them around
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* during optimization, which is why we use "volatile" pointers.
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*/
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static inline unsigned int
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___ia64_inb (unsigned long port)
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{
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volatile unsigned char *addr = __ia64_mk_io_addr(port);
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unsigned char ret;
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ret = *addr;
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__ia64_mf_a();
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return ret;
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}
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static inline unsigned int
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___ia64_inw (unsigned long port)
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{
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volatile unsigned short *addr = __ia64_mk_io_addr(port);
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unsigned short ret;
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ret = *addr;
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__ia64_mf_a();
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return ret;
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}
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static inline unsigned int
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___ia64_inl (unsigned long port)
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{
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volatile unsigned int *addr = __ia64_mk_io_addr(port);
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unsigned int ret;
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ret = *addr;
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__ia64_mf_a();
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return ret;
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}
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static inline void
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___ia64_outb (unsigned char val, unsigned long port)
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{
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volatile unsigned char *addr = __ia64_mk_io_addr(port);
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*addr = val;
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__ia64_mf_a();
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}
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static inline void
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___ia64_outw (unsigned short val, unsigned long port)
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{
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volatile unsigned short *addr = __ia64_mk_io_addr(port);
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*addr = val;
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__ia64_mf_a();
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}
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static inline void
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___ia64_outl (unsigned int val, unsigned long port)
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{
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volatile unsigned int *addr = __ia64_mk_io_addr(port);
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*addr = val;
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__ia64_mf_a();
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}
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static inline void
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__insb (unsigned long port, void *dst, unsigned long count)
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{
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unsigned char *dp = dst;
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while (count--)
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*dp++ = platform_inb(port);
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}
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static inline void
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__insw (unsigned long port, void *dst, unsigned long count)
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{
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unsigned short *dp = dst;
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while (count--)
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*dp++ = platform_inw(port);
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}
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static inline void
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__insl (unsigned long port, void *dst, unsigned long count)
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{
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unsigned int *dp = dst;
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while (count--)
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*dp++ = platform_inl(port);
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}
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static inline void
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__outsb (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned char *sp = src;
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while (count--)
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platform_outb(*sp++, port);
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}
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static inline void
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__outsw (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned short *sp = src;
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while (count--)
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platform_outw(*sp++, port);
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}
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static inline void
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__outsl (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned int *sp = src;
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while (count--)
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platform_outl(*sp++, port);
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}
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/*
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* Unfortunately, some platforms are broken and do not follow the IA-64 architecture
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* specification regarding legacy I/O support. Thus, we have to make these operations
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* platform dependent...
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*/
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#define __inb platform_inb
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#define __inw platform_inw
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#define __inl platform_inl
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#define __outb platform_outb
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#define __outw platform_outw
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#define __outl platform_outl
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#define __mmiowb platform_mmiowb
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#define inb(p) __inb(p)
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#define inw(p) __inw(p)
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#define inl(p) __inl(p)
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#define insb(p,d,c) __insb(p,d,c)
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#define insw(p,d,c) __insw(p,d,c)
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#define insl(p,d,c) __insl(p,d,c)
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#define outb(v,p) __outb(v,p)
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#define outw(v,p) __outw(v,p)
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#define outl(v,p) __outl(v,p)
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#define outsb(p,s,c) __outsb(p,s,c)
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#define outsw(p,s,c) __outsw(p,s,c)
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#define outsl(p,s,c) __outsl(p,s,c)
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#define mmiowb() __mmiowb()
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/*
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* The address passed to these functions are ioremap()ped already.
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*
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* We need these to be machine vectors since some platforms don't provide
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* DMA coherence via PIO reads (PCI drivers and the spec imply that this is
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* a good idea). Writes are ok though for all existing ia64 platforms (and
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* hopefully it'll stay that way).
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*/
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static inline unsigned char
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___ia64_readb (const volatile void __iomem *addr)
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{
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return *(volatile unsigned char __force *)addr;
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}
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static inline unsigned short
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___ia64_readw (const volatile void __iomem *addr)
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{
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return *(volatile unsigned short __force *)addr;
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}
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static inline unsigned int
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___ia64_readl (const volatile void __iomem *addr)
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{
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return *(volatile unsigned int __force *) addr;
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}
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static inline unsigned long
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___ia64_readq (const volatile void __iomem *addr)
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{
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return *(volatile unsigned long __force *) addr;
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}
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static inline void
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__writeb (unsigned char val, volatile void __iomem *addr)
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{
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*(volatile unsigned char __force *) addr = val;
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}
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static inline void
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__writew (unsigned short val, volatile void __iomem *addr)
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{
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*(volatile unsigned short __force *) addr = val;
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}
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static inline void
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__writel (unsigned int val, volatile void __iomem *addr)
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{
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*(volatile unsigned int __force *) addr = val;
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}
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static inline void
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__writeq (unsigned long val, volatile void __iomem *addr)
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{
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*(volatile unsigned long __force *) addr = val;
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}
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#define __readb platform_readb
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#define __readw platform_readw
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#define __readl platform_readl
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#define __readq platform_readq
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#define __readb_relaxed platform_readb_relaxed
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#define __readw_relaxed platform_readw_relaxed
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#define __readl_relaxed platform_readl_relaxed
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#define __readq_relaxed platform_readq_relaxed
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#define readb(a) __readb((a))
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#define readw(a) __readw((a))
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#define readl(a) __readl((a))
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#define readq(a) __readq((a))
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#define readb_relaxed(a) __readb_relaxed((a))
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#define readw_relaxed(a) __readw_relaxed((a))
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#define readl_relaxed(a) __readl_relaxed((a))
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#define readq_relaxed(a) __readq_relaxed((a))
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define __raw_readq readq
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#define __raw_readb_relaxed readb_relaxed
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#define __raw_readw_relaxed readw_relaxed
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#define __raw_readl_relaxed readl_relaxed
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#define __raw_readq_relaxed readq_relaxed
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#define writeb(v,a) __writeb((v), (a))
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#define writew(v,a) __writew((v), (a))
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#define writel(v,a) __writel((v), (a))
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#define writeq(v,a) __writeq((v), (a))
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define __raw_writeq writeq
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#ifndef inb_p
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# define inb_p inb
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#endif
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#ifndef inw_p
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# define inw_p inw
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#endif
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#ifndef inl_p
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# define inl_p inl
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#endif
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#ifndef outb_p
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# define outb_p outb
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#endif
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#ifndef outw_p
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# define outw_p outw
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#endif
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#ifndef outl_p
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# define outl_p outl
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#endif
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extern void __iomem * ioremap(unsigned long offset, unsigned long size);
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extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
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static inline void
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iounmap (volatile void __iomem *addr)
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{
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}
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/* Use normal IO mappings for DMI */
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#define dmi_ioremap ioremap
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#define dmi_iounmap(x,l) iounmap(x)
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#define dmi_alloc(l) kmalloc(l, GFP_ATOMIC)
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# ifdef __KERNEL__
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/*
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* String version of IO memory access ops:
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*/
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extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
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extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
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extern void memset_io(volatile void __iomem *s, int c, long n);
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#define dma_cache_inv(_start,_size) do { } while (0)
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#define dma_cache_wback(_start,_size) do { } while (0)
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#define dma_cache_wback_inv(_start,_size) do { } while (0)
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# endif /* __KERNEL__ */
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/*
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* Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
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* BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
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* On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
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* SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
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* over BIO-level virtual merging.
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*/
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extern unsigned long ia64_max_iommu_merge_mask;
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#if 1
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#define BIO_VMERGE_BOUNDARY 0
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#else
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/*
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* It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
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* replaced by dma_merge_mask() or something of that sort. Note: the only way
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* BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
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* expanded into:
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*
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* addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
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*
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* which is precisely what we want.
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*/
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#define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
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#endif
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#endif /* _ASM_IA64_IO_H */
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