mirror of
https://github.com/torvalds/linux.git
synced 2024-11-10 14:11:52 +00:00
902861e34c
from hotplugged memory rather than only from main memory. Series
"implement "memmap on memory" feature on s390".
- More folio conversions from Matthew Wilcox in the series
"Convert memcontrol charge moving to use folios"
"mm: convert mm counter to take a folio"
- Chengming Zhou has optimized zswap's rbtree locking, providing
significant reductions in system time and modest but measurable
reductions in overall runtimes. The series is "mm/zswap: optimize the
scalability of zswap rb-tree".
- Chengming Zhou has also provided the series "mm/zswap: optimize zswap
lru list" which provides measurable runtime benefits in some
swap-intensive situations.
- And Chengming Zhou further optimizes zswap in the series "mm/zswap:
optimize for dynamic zswap_pools". Measured improvements are modest.
- zswap cleanups and simplifications from Yosry Ahmed in the series "mm:
zswap: simplify zswap_swapoff()".
- In the series "Add DAX ABI for memmap_on_memory", Vishal Verma has
contributed several DAX cleanups as well as adding a sysfs tunable to
control the memmap_on_memory setting when the dax device is hotplugged
as system memory.
- Johannes Weiner has added the large series "mm: zswap: cleanups",
which does that.
- More DAMON work from SeongJae Park in the series
"mm/damon: make DAMON debugfs interface deprecation unignorable"
"selftests/damon: add more tests for core functionalities and corner cases"
"Docs/mm/damon: misc readability improvements"
"mm/damon: let DAMOS feeds and tame/auto-tune itself"
- In the series "mm/mempolicy: weighted interleave mempolicy and sysfs
extension" Rakie Kim has developed a new mempolicy interleaving policy
wherein we allocate memory across nodes in a weighted fashion rather
than uniformly. This is beneficial in heterogeneous memory environments
appearing with CXL.
- Christophe Leroy has contributed some cleanup and consolidation work
against the ARM pagetable dumping code in the series "mm: ptdump:
Refactor CONFIG_DEBUG_WX and check_wx_pages debugfs attribute".
- Luis Chamberlain has added some additional xarray selftesting in the
series "test_xarray: advanced API multi-index tests".
- Muhammad Usama Anjum has reworked the selftest code to make its
human-readable output conform to the TAP ("Test Anything Protocol")
format. Amongst other things, this opens up the use of third-party
tools to parse and process out selftesting results.
- Ryan Roberts has added fork()-time PTE batching of THP ptes in the
series "mm/memory: optimize fork() with PTE-mapped THP". Mainly
targeted at arm64, this significantly speeds up fork() when the process
has a large number of pte-mapped folios.
- David Hildenbrand also gets in on the THP pte batching game in his
series "mm/memory: optimize unmap/zap with PTE-mapped THP". It
implements batching during munmap() and other pte teardown situations.
The microbenchmark improvements are nice.
- And in the series "Transparent Contiguous PTEs for User Mappings" Ryan
Roberts further utilizes arm's pte's contiguous bit ("contpte
mappings"). Kernel build times on arm64 improved nicely. Ryan's series
"Address some contpte nits" provides some followup work.
- In the series "mm/hugetlb: Restore the reservation" Breno Leitao has
fixed an obscure hugetlb race which was causing unnecessary page faults.
He has also added a reproducer under the selftest code.
- In the series "selftests/mm: Output cleanups for the compaction test",
Mark Brown did what the title claims.
- Kinsey Ho has added the series "mm/mglru: code cleanup and refactoring".
- Even more zswap material from Nhat Pham. The series "fix and extend
zswap kselftests" does as claimed.
- In the series "Introduce cpu_dcache_is_aliasing() to fix DAX
regression" Mathieu Desnoyers has cleaned up and fixed rather a mess in
our handling of DAX on archiecctures which have virtually aliasing data
caches. The arm architecture is the main beneficiary.
- Lokesh Gidra's series "per-vma locks in userfaultfd" provides dramatic
improvements in worst-case mmap_lock hold times during certain
userfaultfd operations.
- Some page_owner enhancements and maintenance work from Oscar Salvador
in his series
"page_owner: print stacks and their outstanding allocations"
"page_owner: Fixup and cleanup"
- Uladzislau Rezki has contributed some vmalloc scalability improvements
in his series "Mitigate a vmap lock contention". It realizes a 12x
improvement for a certain microbenchmark.
- Some kexec/crash cleanup work from Baoquan He in the series "Split
crash out from kexec and clean up related config items".
- Some zsmalloc maintenance work from Chengming Zhou in the series
"mm/zsmalloc: fix and optimize objects/page migration"
"mm/zsmalloc: some cleanup for get/set_zspage_mapping()"
- Zi Yan has taught the MM to perform compaction on folios larger than
order=0. This a step along the path to implementaton of the merging of
large anonymous folios. The series is named "Enable >0 order folio
memory compaction".
- Christoph Hellwig has done quite a lot of cleanup work in the
pagecache writeback code in his series "convert write_cache_pages() to
an iterator".
- Some modest hugetlb cleanups and speedups in Vishal Moola's series
"Handle hugetlb faults under the VMA lock".
- Zi Yan has changed the page splitting code so we can split huge pages
into sizes other than order-0 to better utilize large folios. The
series is named "Split a folio to any lower order folios".
- David Hildenbrand has contributed the series "mm: remove
total_mapcount()", a cleanup.
- Matthew Wilcox has sought to improve the performance of bulk memory
freeing in his series "Rearrange batched folio freeing".
- Gang Li's series "hugetlb: parallelize hugetlb page init on boot"
provides large improvements in bootup times on large machines which are
configured to use large numbers of hugetlb pages.
- Matthew Wilcox's series "PageFlags cleanups" does that.
- Qi Zheng's series "minor fixes and supplement for ptdesc" does that
also. S390 is affected.
- Cleanups to our pagemap utility functions from Peter Xu in his series
"mm/treewide: Replace pXd_large() with pXd_leaf()".
- Nico Pache has fixed a few things with our hugepage selftests in his
series "selftests/mm: Improve Hugepage Test Handling in MM Selftests".
- Also, of course, many singleton patches to many things. Please see
the individual changelogs for details.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQTTMBEPP41GrTpTJgfdBJ7gKXxAjgUCZfJpPQAKCRDdBJ7gKXxA
joxeAP9TrcMEuHnLmBlhIXkWbIR4+ki+pA3v+gNTlJiBhnfVSgD9G55t1aBaRplx
TMNhHfyiHYDTx/GAV9NXW84tasJSDgA=
=TG55
-----END PGP SIGNATURE-----
Merge tag 'mm-stable-2024-03-13-20-04' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
Pull MM updates from Andrew Morton:
- Sumanth Korikkar has taught s390 to allocate hotplug-time page frames
from hotplugged memory rather than only from main memory. Series
"implement "memmap on memory" feature on s390".
- More folio conversions from Matthew Wilcox in the series
"Convert memcontrol charge moving to use folios"
"mm: convert mm counter to take a folio"
- Chengming Zhou has optimized zswap's rbtree locking, providing
significant reductions in system time and modest but measurable
reductions in overall runtimes. The series is "mm/zswap: optimize the
scalability of zswap rb-tree".
- Chengming Zhou has also provided the series "mm/zswap: optimize zswap
lru list" which provides measurable runtime benefits in some
swap-intensive situations.
- And Chengming Zhou further optimizes zswap in the series "mm/zswap:
optimize for dynamic zswap_pools". Measured improvements are modest.
- zswap cleanups and simplifications from Yosry Ahmed in the series
"mm: zswap: simplify zswap_swapoff()".
- In the series "Add DAX ABI for memmap_on_memory", Vishal Verma has
contributed several DAX cleanups as well as adding a sysfs tunable to
control the memmap_on_memory setting when the dax device is
hotplugged as system memory.
- Johannes Weiner has added the large series "mm: zswap: cleanups",
which does that.
- More DAMON work from SeongJae Park in the series
"mm/damon: make DAMON debugfs interface deprecation unignorable"
"selftests/damon: add more tests for core functionalities and corner cases"
"Docs/mm/damon: misc readability improvements"
"mm/damon: let DAMOS feeds and tame/auto-tune itself"
- In the series "mm/mempolicy: weighted interleave mempolicy and sysfs
extension" Rakie Kim has developed a new mempolicy interleaving
policy wherein we allocate memory across nodes in a weighted fashion
rather than uniformly. This is beneficial in heterogeneous memory
environments appearing with CXL.
- Christophe Leroy has contributed some cleanup and consolidation work
against the ARM pagetable dumping code in the series "mm: ptdump:
Refactor CONFIG_DEBUG_WX and check_wx_pages debugfs attribute".
- Luis Chamberlain has added some additional xarray selftesting in the
series "test_xarray: advanced API multi-index tests".
- Muhammad Usama Anjum has reworked the selftest code to make its
human-readable output conform to the TAP ("Test Anything Protocol")
format. Amongst other things, this opens up the use of third-party
tools to parse and process out selftesting results.
- Ryan Roberts has added fork()-time PTE batching of THP ptes in the
series "mm/memory: optimize fork() with PTE-mapped THP". Mainly
targeted at arm64, this significantly speeds up fork() when the
process has a large number of pte-mapped folios.
- David Hildenbrand also gets in on the THP pte batching game in his
series "mm/memory: optimize unmap/zap with PTE-mapped THP". It
implements batching during munmap() and other pte teardown
situations. The microbenchmark improvements are nice.
- And in the series "Transparent Contiguous PTEs for User Mappings"
Ryan Roberts further utilizes arm's pte's contiguous bit ("contpte
mappings"). Kernel build times on arm64 improved nicely. Ryan's
series "Address some contpte nits" provides some followup work.
- In the series "mm/hugetlb: Restore the reservation" Breno Leitao has
fixed an obscure hugetlb race which was causing unnecessary page
faults. He has also added a reproducer under the selftest code.
- In the series "selftests/mm: Output cleanups for the compaction
test", Mark Brown did what the title claims.
- Kinsey Ho has added the series "mm/mglru: code cleanup and
refactoring".
- Even more zswap material from Nhat Pham. The series "fix and extend
zswap kselftests" does as claimed.
- In the series "Introduce cpu_dcache_is_aliasing() to fix DAX
regression" Mathieu Desnoyers has cleaned up and fixed rather a mess
in our handling of DAX on archiecctures which have virtually aliasing
data caches. The arm architecture is the main beneficiary.
- Lokesh Gidra's series "per-vma locks in userfaultfd" provides
dramatic improvements in worst-case mmap_lock hold times during
certain userfaultfd operations.
- Some page_owner enhancements and maintenance work from Oscar Salvador
in his series
"page_owner: print stacks and their outstanding allocations"
"page_owner: Fixup and cleanup"
- Uladzislau Rezki has contributed some vmalloc scalability
improvements in his series "Mitigate a vmap lock contention". It
realizes a 12x improvement for a certain microbenchmark.
- Some kexec/crash cleanup work from Baoquan He in the series "Split
crash out from kexec and clean up related config items".
- Some zsmalloc maintenance work from Chengming Zhou in the series
"mm/zsmalloc: fix and optimize objects/page migration"
"mm/zsmalloc: some cleanup for get/set_zspage_mapping()"
- Zi Yan has taught the MM to perform compaction on folios larger than
order=0. This a step along the path to implementaton of the merging
of large anonymous folios. The series is named "Enable >0 order folio
memory compaction".
- Christoph Hellwig has done quite a lot of cleanup work in the
pagecache writeback code in his series "convert write_cache_pages()
to an iterator".
- Some modest hugetlb cleanups and speedups in Vishal Moola's series
"Handle hugetlb faults under the VMA lock".
- Zi Yan has changed the page splitting code so we can split huge pages
into sizes other than order-0 to better utilize large folios. The
series is named "Split a folio to any lower order folios".
- David Hildenbrand has contributed the series "mm: remove
total_mapcount()", a cleanup.
- Matthew Wilcox has sought to improve the performance of bulk memory
freeing in his series "Rearrange batched folio freeing".
- Gang Li's series "hugetlb: parallelize hugetlb page init on boot"
provides large improvements in bootup times on large machines which
are configured to use large numbers of hugetlb pages.
- Matthew Wilcox's series "PageFlags cleanups" does that.
- Qi Zheng's series "minor fixes and supplement for ptdesc" does that
also. S390 is affected.
- Cleanups to our pagemap utility functions from Peter Xu in his series
"mm/treewide: Replace pXd_large() with pXd_leaf()".
- Nico Pache has fixed a few things with our hugepage selftests in his
series "selftests/mm: Improve Hugepage Test Handling in MM
Selftests".
- Also, of course, many singleton patches to many things. Please see
the individual changelogs for details.
* tag 'mm-stable-2024-03-13-20-04' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: (435 commits)
mm/zswap: remove the memcpy if acomp is not sleepable
crypto: introduce: acomp_is_async to expose if comp drivers might sleep
memtest: use {READ,WRITE}_ONCE in memory scanning
mm: prohibit the last subpage from reusing the entire large folio
mm: recover pud_leaf() definitions in nopmd case
selftests/mm: skip the hugetlb-madvise tests on unmet hugepage requirements
selftests/mm: skip uffd hugetlb tests with insufficient hugepages
selftests/mm: dont fail testsuite due to a lack of hugepages
mm/huge_memory: skip invalid debugfs new_order input for folio split
mm/huge_memory: check new folio order when split a folio
mm, vmscan: retry kswapd's priority loop with cache_trim_mode off on failure
mm: add an explicit smp_wmb() to UFFDIO_CONTINUE
mm: fix list corruption in put_pages_list
mm: remove folio from deferred split list before uncharging it
filemap: avoid unnecessary major faults in filemap_fault()
mm,page_owner: drop unnecessary check
mm,page_owner: check for null stack_record before bumping its refcount
mm: swap: fix race between free_swap_and_cache() and swapoff()
mm/treewide: align up pXd_leaf() retval across archs
mm/treewide: drop pXd_large()
...
816 lines
24 KiB
Plaintext
816 lines
24 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config XTENSA
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def_bool y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_CPU_CACHE_ALIASING
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select ARCH_HAS_BINFMT_FLAT if !MMU
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select ARCH_HAS_CURRENT_STACK_POINTER
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select ARCH_HAS_DMA_PREP_COHERENT if MMU
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_KCOV
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select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
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select ARCH_HAS_DMA_SET_UNCACHED if MMU
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select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
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select ARCH_HAS_STRNLEN_USER
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select ARCH_USE_MEMTEST
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_WANT_IPC_PARSE_VERSION
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select BUILDTIME_TABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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select DMA_NONCOHERENT_MMAP if MMU
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select GENERIC_ATOMIC64
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select GENERIC_IRQ_SHOW
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select GENERIC_LIB_CMPDI2
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select GENERIC_LIB_MULDI3
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select GENERIC_LIB_UCMPDI2
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select GENERIC_PCI_IOMAP
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select GENERIC_SCHED_CLOCK
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select GENERIC_IOREMAP if MMU
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
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select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
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select HAVE_ARCH_KCSAN
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_ASM_MODVERSIONS
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select HAVE_CONTEXT_TRACKING_USER
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_CONTIGUOUS
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select HAVE_EXIT_THREAD
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select HAVE_FUNCTION_TRACER
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select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000
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select HAVE_HW_BREAKPOINT if PERF_EVENTS
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select HAVE_IRQ_TIME_ACCOUNTING
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select HAVE_PAGE_SIZE_4KB
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select HAVE_PCI
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select HAVE_PERF_EVENTS
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select HAVE_STACKPROTECTOR
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select HAVE_SYSCALL_TRACEPOINTS
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select IRQ_DOMAIN
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select LOCK_MM_AND_FIND_VMA
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select MODULES_USE_ELF_RELA
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select PERF_USE_VMALLOC
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select TRACE_IRQFLAGS_SUPPORT
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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primarily for embedded systems. These processors are both
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configurable and extensible. The Linux port to the Xtensa
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architecture supports all processor configurations and extensions,
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with reasonable minimum requirements. The Xtensa Linux project has
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a home page at <http://www.linux-xtensa.org/>.
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config GENERIC_HWEIGHT
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def_bool y
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config ARCH_HAS_ILOG2_U32
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def_bool n
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config ARCH_HAS_ILOG2_U64
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def_bool n
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config ARCH_MTD_XIP
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def_bool y
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config NO_IOPORT_MAP
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def_bool n
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config HZ
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int
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default 100
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config LOCKDEP_SUPPORT
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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config MMU
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def_bool n
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select PFAULT
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config HAVE_XTENSA_GPIO32
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def_bool n
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config KASAN_SHADOW_OFFSET
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hex
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default 0x6e400000
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config CPU_BIG_ENDIAN
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def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
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config CPU_LITTLE_ENDIAN
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def_bool !CPU_BIG_ENDIAN
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|
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config CC_HAVE_CALL0_ABI
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def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1)
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|
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menu "Processor type and features"
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choice
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prompt "Xtensa Processor Configuration"
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default XTENSA_VARIANT_FSF
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config XTENSA_VARIANT_FSF
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bool "fsf - default (not generic) configuration"
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select MMU
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config XTENSA_VARIANT_DC232B
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bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
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select MMU
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select HAVE_XTENSA_GPIO32
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help
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This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
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config XTENSA_VARIANT_DC233C
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bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
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select MMU
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select HAVE_XTENSA_GPIO32
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help
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This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
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|
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config XTENSA_VARIANT_CUSTOM
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bool "Custom Xtensa processor configuration"
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select HAVE_XTENSA_GPIO32
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help
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Select this variant to use a custom Xtensa processor configuration.
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You will be prompted for a processor variant CORENAME.
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endchoice
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config XTENSA_VARIANT_CUSTOM_NAME
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string "Xtensa Processor Custom Core Variant Name"
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depends on XTENSA_VARIANT_CUSTOM
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help
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Provide the name of a custom Xtensa processor variant.
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This CORENAME selects arch/xtensa/variants/CORENAME.
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Don't forget you have to select MMU if you have one.
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config XTENSA_VARIANT_NAME
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string
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default "dc232b" if XTENSA_VARIANT_DC232B
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default "dc233c" if XTENSA_VARIANT_DC233C
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default "fsf" if XTENSA_VARIANT_FSF
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default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
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config XTENSA_VARIANT_MMU
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bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
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depends on XTENSA_VARIANT_CUSTOM
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default y
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select MMU
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help
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Build a Conventional Kernel with full MMU support,
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ie: it supports a TLB with auto-loading, page protection.
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config XTENSA_VARIANT_HAVE_PERF_EVENTS
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bool "Core variant has Performance Monitor Module"
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depends on XTENSA_VARIANT_CUSTOM
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default n
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help
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Enable if core variant has Performance Monitor Module with
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External Registers Interface.
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If unsure, say N.
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config XTENSA_FAKE_NMI
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bool "Treat PMM IRQ as NMI"
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depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
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default n
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help
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If PMM IRQ is the only IRQ at EXCM level it is safe to
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treat it as NMI, which improves accuracy of profiling.
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If there are other interrupts at or above PMM IRQ priority level
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but not above the EXCM level, PMM IRQ still may be treated as NMI,
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but only if these IRQs are not used. There will be a build warning
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saying that this is not safe, and a bugcheck if one of these IRQs
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actually fire.
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If unsure, say N.
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|
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config PFAULT
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bool "Handle protection faults" if EXPERT && !MMU
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default y
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help
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Handle protection faults. MMU configurations must enable it.
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noMMU configurations may disable it if used memory map never
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generates protection faults or faults are always fatal.
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If unsure, say Y.
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config XTENSA_UNALIGNED_USER
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bool "Unaligned memory access in user space"
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help
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|
The Xtensa architecture currently does not handle unaligned
|
|
memory accesses in hardware but through an exception handler.
|
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Per default, unaligned memory accesses are disabled in user space.
|
|
|
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Say Y here to enable unaligned memory access in user space.
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|
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config XTENSA_LOAD_STORE
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bool "Load/store exception handler for memory only readable with l32"
|
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help
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|
The Xtensa architecture only allows reading memory attached to its
|
|
instruction bus with l32r and l32i instructions, all other
|
|
instructions raise an exception with the LoadStoreErrorCause code.
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This makes it hard to use some configurations, e.g. store string
|
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literals in FLASH memory attached to the instruction bus.
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Say Y here to enable exception handler that allows transparent
|
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byte and 2-byte access to memory attached to instruction bus.
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config HAVE_SMP
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bool "System Supports SMP (MX)"
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depends on XTENSA_VARIANT_CUSTOM
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select XTENSA_MX
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help
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|
This option is used to indicate that the system-on-a-chip (SOC)
|
|
supports Multiprocessing. Multiprocessor support implemented above
|
|
the CPU core definition and currently needs to be selected manually.
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Multiprocessor support is implemented with external cache and
|
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interrupt controllers.
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The MX interrupt distributer adds Interprocessor Interrupts
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and causes the IRQ numbers to be increased by 4 for devices
|
|
like the open cores ethernet driver and the serial interface.
|
|
|
|
You still have to select "Enable SMP" to enable SMP on this SOC.
|
|
|
|
config SMP
|
|
bool "Enable Symmetric multi-processing support"
|
|
depends on HAVE_SMP
|
|
select GENERIC_SMP_IDLE_THREAD
|
|
help
|
|
Enabled SMP Software; allows more than one CPU/CORE
|
|
to be activated during startup.
|
|
|
|
config NR_CPUS
|
|
depends on SMP
|
|
int "Maximum number of CPUs (2-32)"
|
|
range 2 32
|
|
default "4"
|
|
|
|
config HOTPLUG_CPU
|
|
bool "Enable CPU hotplug support"
|
|
depends on SMP
|
|
help
|
|
Say Y here to allow turning CPUs off and on. CPUs can be
|
|
controlled through /sys/devices/system/cpu.
|
|
|
|
Say N if you want to disable CPU hotplug.
|
|
|
|
config SECONDARY_RESET_VECTOR
|
|
bool "Secondary cores use alternative reset vector"
|
|
default y
|
|
depends on HAVE_SMP
|
|
help
|
|
Secondary cores may be configured to use alternative reset vector,
|
|
or all cores may use primary reset vector.
|
|
Say Y here to supply handler for the alternative reset location.
|
|
|
|
config FAST_SYSCALL_XTENSA
|
|
bool "Enable fast atomic syscalls"
|
|
default n
|
|
help
|
|
fast_syscall_xtensa is a syscall that can make atomic operations
|
|
on UP kernel when processor has no s32c1i support.
|
|
|
|
This syscall is deprecated. It may have issues when called with
|
|
invalid arguments. It is provided only for backwards compatibility.
|
|
Only enable it if your userspace software requires it.
|
|
|
|
If unsure, say N.
|
|
|
|
config FAST_SYSCALL_SPILL_REGISTERS
|
|
bool "Enable spill registers syscall"
|
|
default n
|
|
help
|
|
fast_syscall_spill_registers is a syscall that spills all active
|
|
register windows of a calling userspace task onto its stack.
|
|
|
|
This syscall is deprecated. It may have issues when called with
|
|
invalid arguments. It is provided only for backwards compatibility.
|
|
Only enable it if your userspace software requires it.
|
|
|
|
If unsure, say N.
|
|
|
|
choice
|
|
prompt "Kernel ABI"
|
|
default KERNEL_ABI_DEFAULT
|
|
help
|
|
Select ABI for the kernel code. This ABI is independent of the
|
|
supported userspace ABI and any combination of the
|
|
kernel/userspace ABI is possible and should work.
|
|
|
|
In case both kernel and userspace support only call0 ABI
|
|
all register windows support code will be omitted from the
|
|
build.
|
|
|
|
If unsure, choose the default ABI.
|
|
|
|
config KERNEL_ABI_DEFAULT
|
|
bool "Default ABI"
|
|
help
|
|
Select this option to compile kernel code with the default ABI
|
|
selected for the toolchain.
|
|
Normally cores with windowed registers option use windowed ABI and
|
|
cores without it use call0 ABI.
|
|
|
|
config KERNEL_ABI_CALL0
|
|
bool "Call0 ABI" if CC_HAVE_CALL0_ABI
|
|
help
|
|
Select this option to compile kernel code with call0 ABI even with
|
|
toolchain that defaults to windowed ABI.
|
|
When this option is not selected the default toolchain ABI will
|
|
be used for the kernel code.
|
|
|
|
endchoice
|
|
|
|
config USER_ABI_CALL0
|
|
bool
|
|
|
|
choice
|
|
prompt "Userspace ABI"
|
|
default USER_ABI_DEFAULT
|
|
help
|
|
Select supported userspace ABI.
|
|
|
|
If unsure, choose the default ABI.
|
|
|
|
config USER_ABI_DEFAULT
|
|
bool "Default ABI only"
|
|
help
|
|
Assume default userspace ABI. For XEA2 cores it is windowed ABI.
|
|
call0 ABI binaries may be run on such kernel, but signal delivery
|
|
will not work correctly for them.
|
|
|
|
config USER_ABI_CALL0_ONLY
|
|
bool "Call0 ABI only"
|
|
select USER_ABI_CALL0
|
|
help
|
|
Select this option to support only call0 ABI in userspace.
|
|
Windowed ABI binaries will crash with a segfault caused by
|
|
an illegal instruction exception on the first 'entry' opcode.
|
|
|
|
Choose this option if you're planning to run only user code
|
|
built with call0 ABI.
|
|
|
|
config USER_ABI_CALL0_PROBE
|
|
bool "Support both windowed and call0 ABI by probing"
|
|
select USER_ABI_CALL0
|
|
help
|
|
Select this option to support both windowed and call0 userspace
|
|
ABIs. When enabled all processes are started with PS.WOE disabled
|
|
and a fast user exception handler for an illegal instruction is
|
|
used to turn on PS.WOE bit on the first 'entry' opcode executed by
|
|
the userspace.
|
|
|
|
This option should be enabled for the kernel that must support
|
|
both call0 and windowed ABIs in userspace at the same time.
|
|
|
|
Note that Xtensa ISA does not guarantee that entry opcode will
|
|
raise an illegal instruction exception on cores with XEA2 when
|
|
PS.WOE is disabled, check whether the target core supports it.
|
|
|
|
endchoice
|
|
|
|
endmenu
|
|
|
|
config XTENSA_CALIBRATE_CCOUNT
|
|
def_bool n
|
|
help
|
|
On some platforms (XT2000, for example), the CPU clock rate can
|
|
vary. The frequency can be determined, however, by measuring
|
|
against a well known, fixed frequency, such as an UART oscillator.
|
|
|
|
config SERIAL_CONSOLE
|
|
def_bool n
|
|
|
|
config PLATFORM_HAVE_XIP
|
|
def_bool n
|
|
|
|
menu "Platform options"
|
|
|
|
choice
|
|
prompt "Xtensa System Type"
|
|
default XTENSA_PLATFORM_ISS
|
|
|
|
config XTENSA_PLATFORM_ISS
|
|
bool "ISS"
|
|
select XTENSA_CALIBRATE_CCOUNT
|
|
select SERIAL_CONSOLE
|
|
help
|
|
ISS is an acronym for Tensilica's Instruction Set Simulator.
|
|
|
|
config XTENSA_PLATFORM_XT2000
|
|
bool "XT2000"
|
|
help
|
|
XT2000 is the name of Tensilica's feature-rich emulation platform.
|
|
This hardware is capable of running a full Linux distribution.
|
|
|
|
config XTENSA_PLATFORM_XTFPGA
|
|
bool "XTFPGA"
|
|
select ETHOC if ETHERNET
|
|
select PLATFORM_WANT_DEFAULT_MEM if !MMU
|
|
select SERIAL_CONSOLE
|
|
select XTENSA_CALIBRATE_CCOUNT
|
|
select PLATFORM_HAVE_XIP
|
|
help
|
|
XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
|
|
This hardware is capable of running a full Linux distribution.
|
|
|
|
endchoice
|
|
|
|
config PLATFORM_NR_IRQS
|
|
int
|
|
default 3 if XTENSA_PLATFORM_XT2000
|
|
default 0
|
|
|
|
config XTENSA_CPU_CLOCK
|
|
int "CPU clock rate [MHz]"
|
|
depends on !XTENSA_CALIBRATE_CCOUNT
|
|
default 16
|
|
|
|
config GENERIC_CALIBRATE_DELAY
|
|
bool "Auto calibration of the BogoMIPS value"
|
|
help
|
|
The BogoMIPS value can easily be derived from the CPU frequency.
|
|
|
|
config CMDLINE_BOOL
|
|
bool "Default bootloader kernel arguments"
|
|
|
|
config CMDLINE
|
|
string "Initial kernel command string"
|
|
depends on CMDLINE_BOOL
|
|
default "console=ttyS0,38400 root=/dev/ram"
|
|
help
|
|
On some architectures (EBSA110 and CATS), there is currently no way
|
|
for the boot loader to pass arguments to the kernel. For these
|
|
architectures, you should supply some command-line options at build
|
|
time by entering them here. As a minimum, you should specify the
|
|
memory size and the root device (e.g., mem=64M root=/dev/nfs).
|
|
|
|
config USE_OF
|
|
bool "Flattened Device Tree support"
|
|
select OF
|
|
select OF_EARLY_FLATTREE
|
|
help
|
|
Include support for flattened device tree machine descriptions.
|
|
|
|
config BUILTIN_DTB_SOURCE
|
|
string "DTB to build into the kernel image"
|
|
depends on OF
|
|
|
|
config PARSE_BOOTPARAM
|
|
bool "Parse bootparam block"
|
|
default y
|
|
help
|
|
Parse parameters passed to the kernel from the bootloader. It may
|
|
be disabled if the kernel is known to run without the bootloader.
|
|
|
|
If unsure, say Y.
|
|
|
|
choice
|
|
prompt "Semihosting interface"
|
|
default XTENSA_SIMCALL_ISS
|
|
depends on XTENSA_PLATFORM_ISS
|
|
help
|
|
Choose semihosting interface that will be used for serial port,
|
|
block device and networking.
|
|
|
|
config XTENSA_SIMCALL_ISS
|
|
bool "simcall"
|
|
help
|
|
Use simcall instruction. simcall is only available on simulators,
|
|
it does nothing on hardware.
|
|
|
|
config XTENSA_SIMCALL_GDBIO
|
|
bool "GDBIO"
|
|
help
|
|
Use break instruction. It is available on real hardware when GDB
|
|
is attached to it via JTAG.
|
|
|
|
endchoice
|
|
|
|
config BLK_DEV_SIMDISK
|
|
tristate "Host file-based simulated block device support"
|
|
default n
|
|
depends on XTENSA_PLATFORM_ISS && BLOCK
|
|
help
|
|
Create block devices that map to files in the host file system.
|
|
Device binding to host file may be changed at runtime via proc
|
|
interface provided the device is not in use.
|
|
|
|
config BLK_DEV_SIMDISK_COUNT
|
|
int "Number of host file-based simulated block devices"
|
|
range 1 10
|
|
depends on BLK_DEV_SIMDISK
|
|
default 2
|
|
help
|
|
This is the default minimal number of created block devices.
|
|
Kernel/module parameter 'simdisk_count' may be used to change this
|
|
value at runtime. More file names (but no more than 10) may be
|
|
specified as parameters, simdisk_count grows accordingly.
|
|
|
|
config SIMDISK0_FILENAME
|
|
string "Host filename for the first simulated device"
|
|
depends on BLK_DEV_SIMDISK = y
|
|
default ""
|
|
help
|
|
Attach a first simdisk to a host file. Conventionally, this file
|
|
contains a root file system.
|
|
|
|
config SIMDISK1_FILENAME
|
|
string "Host filename for the second simulated device"
|
|
depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
|
|
default ""
|
|
help
|
|
Another simulated disk in a host file for a buildroot-independent
|
|
storage.
|
|
|
|
config XTFPGA_LCD
|
|
bool "Enable XTFPGA LCD driver"
|
|
depends on XTENSA_PLATFORM_XTFPGA
|
|
default n
|
|
help
|
|
There's a 2x16 LCD on most of XTFPGA boards, kernel may output
|
|
progress messages there during bootup/shutdown. It may be useful
|
|
during board bringup.
|
|
|
|
If unsure, say N.
|
|
|
|
config XTFPGA_LCD_BASE_ADDR
|
|
hex "XTFPGA LCD base address"
|
|
depends on XTFPGA_LCD
|
|
default "0x0d0c0000"
|
|
help
|
|
Base address of the LCD controller inside KIO region.
|
|
Different boards from XTFPGA family have LCD controller at different
|
|
addresses. Please consult prototyping user guide for your board for
|
|
the correct address. Wrong address here may lead to hardware lockup.
|
|
|
|
config XTFPGA_LCD_8BIT_ACCESS
|
|
bool "Use 8-bit access to XTFPGA LCD"
|
|
depends on XTFPGA_LCD
|
|
default n
|
|
help
|
|
LCD may be connected with 4- or 8-bit interface, 8-bit access may
|
|
only be used with 8-bit interface. Please consult prototyping user
|
|
guide for your board for the correct interface width.
|
|
|
|
comment "Kernel memory layout"
|
|
|
|
config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
bool "Initialize Xtensa MMU inside the Linux kernel code"
|
|
depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
|
|
default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
|
|
help
|
|
Earlier version initialized the MMU in the exception vector
|
|
before jumping to _startup in head.S and had an advantage that
|
|
it was possible to place a software breakpoint at 'reset' and
|
|
then enter your normal kernel breakpoints once the MMU was mapped
|
|
to the kernel mappings (0XC0000000).
|
|
|
|
This unfortunately won't work for U-Boot and likely also won't
|
|
work for using KEXEC to have a hot kernel ready for doing a
|
|
KDUMP.
|
|
|
|
So now the MMU is initialized in head.S but it's necessary to
|
|
use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
|
|
xt-gdb can't place a Software Breakpoint in the 0XD region prior
|
|
to mapping the MMU and after mapping even if the area of low memory
|
|
was mapped gdb wouldn't remove the breakpoint on hitting it as the
|
|
PC wouldn't match. Since Hardware Breakpoints are recommended for
|
|
Linux configurations it seems reasonable to just assume they exist
|
|
and leave this older mechanism for unfortunate souls that choose
|
|
not to follow Tensilica's recommendation.
|
|
|
|
Selecting this will cause U-Boot to set the KERNEL Load and Entry
|
|
address at 0x00003000 instead of the mapped std of 0xD0003000.
|
|
|
|
If in doubt, say Y.
|
|
|
|
config XIP_KERNEL
|
|
bool "Kernel Execute-In-Place from ROM"
|
|
depends on PLATFORM_HAVE_XIP
|
|
help
|
|
Execute-In-Place allows the kernel to run from non-volatile storage
|
|
directly addressable by the CPU, such as NOR flash. This saves RAM
|
|
space since the text section of the kernel is not loaded from flash
|
|
to RAM. Read-write sections, such as the data section and stack,
|
|
are still copied to RAM. The XIP kernel is not compressed since
|
|
it has to run directly from flash, so it will take more space to
|
|
store it. The flash address used to link the kernel object files,
|
|
and for storing it, is configuration dependent. Therefore, if you
|
|
say Y here, you must know the proper physical address where to
|
|
store the kernel image depending on your own flash memory usage.
|
|
|
|
Also note that the make target becomes "make xipImage" rather than
|
|
"make Image" or "make uImage". The final kernel binary to put in
|
|
ROM memory will be arch/xtensa/boot/xipImage.
|
|
|
|
If unsure, say N.
|
|
|
|
config MEMMAP_CACHEATTR
|
|
hex "Cache attributes for the memory address space"
|
|
depends on !MMU
|
|
default 0x22222222
|
|
help
|
|
These cache attributes are set up for noMMU systems. Each hex digit
|
|
specifies cache attributes for the corresponding 512MB memory
|
|
region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
|
|
bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
|
|
|
|
Cache attribute values are specific for the MMU type.
|
|
For region protection MMUs:
|
|
1: WT cached,
|
|
2: cache bypass,
|
|
4: WB cached,
|
|
f: illegal.
|
|
For full MMU:
|
|
bit 0: executable,
|
|
bit 1: writable,
|
|
bits 2..3:
|
|
0: cache bypass,
|
|
1: WB cache,
|
|
2: WT cache,
|
|
3: special (c and e are illegal, f is reserved).
|
|
For MPU:
|
|
0: illegal,
|
|
1: WB cache,
|
|
2: WB, no-write-allocate cache,
|
|
3: WT cache,
|
|
4: cache bypass.
|
|
|
|
config KSEG_PADDR
|
|
hex "Physical address of the KSEG mapping"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
|
|
default 0x00000000
|
|
help
|
|
This is the physical address where KSEG is mapped. Please refer to
|
|
the chosen KSEG layout help for the required address alignment.
|
|
Unpacked kernel image (including vectors) must be located completely
|
|
within KSEG.
|
|
Physical memory below this address is not available to linux.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
config KERNEL_VIRTUAL_ADDRESS
|
|
hex "Kernel virtual address"
|
|
depends on MMU && XIP_KERNEL
|
|
default 0xd0003000
|
|
help
|
|
This is the virtual address where the XIP kernel is mapped.
|
|
XIP kernel may be mapped into KSEG or KIO region, virtual address
|
|
provided here must match kernel load address provided in
|
|
KERNEL_LOAD_ADDRESS.
|
|
|
|
config KERNEL_LOAD_ADDRESS
|
|
hex "Kernel load address"
|
|
default 0x60003000 if !MMU
|
|
default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
This is the address where the kernel is loaded.
|
|
It is virtual address for MMUv2 configurations and physical address
|
|
for all other configurations.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
choice
|
|
prompt "Relocatable vectors location"
|
|
default XTENSA_VECTORS_IN_TEXT
|
|
help
|
|
Choose whether relocatable vectors are merged into the kernel .text
|
|
or placed separately at runtime. This option does not affect
|
|
configurations without VECBASE register where vectors are always
|
|
placed at their hardware-defined locations.
|
|
|
|
config XTENSA_VECTORS_IN_TEXT
|
|
bool "Merge relocatable vectors into kernel text"
|
|
depends on !MTD_XIP
|
|
help
|
|
This option puts relocatable vectors into the kernel .text section
|
|
with proper alignment.
|
|
This is a safe choice for most configurations.
|
|
|
|
config XTENSA_VECTORS_SEPARATE
|
|
bool "Put relocatable vectors at fixed address"
|
|
help
|
|
This option puts relocatable vectors at specific virtual address.
|
|
Vectors are merged with the .init data in the kernel image and
|
|
are copied into their designated location during kernel startup.
|
|
Use it to put vectors into IRAM or out of FLASH on kernels with
|
|
XIP-aware MTD support.
|
|
|
|
endchoice
|
|
|
|
config VECTORS_ADDR
|
|
hex "Kernel vectors virtual address"
|
|
default 0x00000000
|
|
depends on XTENSA_VECTORS_SEPARATE
|
|
help
|
|
This is the virtual address of the (relocatable) vectors base.
|
|
It must be within KSEG if MMU is used.
|
|
|
|
config XIP_DATA_ADDR
|
|
hex "XIP kernel data virtual address"
|
|
depends on XIP_KERNEL
|
|
default 0x00000000
|
|
help
|
|
This is the virtual address where XIP kernel data is copied.
|
|
It must be within KSEG if MMU is used.
|
|
|
|
config PLATFORM_WANT_DEFAULT_MEM
|
|
def_bool n
|
|
|
|
config DEFAULT_MEM_START
|
|
hex
|
|
prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
|
|
default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
|
|
default 0x00000000
|
|
help
|
|
This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
|
|
in noMMU configurations.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
choice
|
|
prompt "KSEG layout"
|
|
depends on MMU
|
|
default XTENSA_KSEG_MMU_V2
|
|
|
|
config XTENSA_KSEG_MMU_V2
|
|
bool "MMUv2: 128MB cached + 128MB uncached"
|
|
help
|
|
MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
|
|
at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
|
|
without cache.
|
|
KSEG_PADDR must be aligned to 128MB.
|
|
|
|
config XTENSA_KSEG_256M
|
|
bool "256MB cached + 256MB uncached"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
|
|
with cache and to 0xc0000000 without cache.
|
|
KSEG_PADDR must be aligned to 256MB.
|
|
|
|
config XTENSA_KSEG_512M
|
|
bool "512MB cached + 512MB uncached"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
|
|
with cache and to 0xc0000000 without cache.
|
|
KSEG_PADDR must be aligned to 256MB.
|
|
|
|
endchoice
|
|
|
|
config HIGHMEM
|
|
bool "High Memory Support"
|
|
depends on MMU
|
|
select KMAP_LOCAL
|
|
help
|
|
Linux can use the full amount of RAM in the system by
|
|
default. However, the default MMUv2 setup only maps the
|
|
lowermost 128 MB of memory linearly to the areas starting
|
|
at 0xd0000000 (cached) and 0xd8000000 (uncached).
|
|
When there are more than 128 MB memory in the system not
|
|
all of it can be "permanently mapped" by the kernel.
|
|
The physical memory that's not permanently mapped is called
|
|
"high memory".
|
|
|
|
If you are compiling a kernel which will never run on a
|
|
machine with more than 128 MB total physical RAM, answer
|
|
N here.
|
|
|
|
If unsure, say Y.
|
|
|
|
config ARCH_FORCE_MAX_ORDER
|
|
int "Order of maximal physically contiguous allocations"
|
|
default "10"
|
|
help
|
|
The kernel page allocator limits the size of maximal physically
|
|
contiguous allocations. The limit is called MAX_PAGE_ORDER and it
|
|
defines the maximal power of two of number of pages that can be
|
|
allocated as a single contiguous block. This option allows
|
|
overriding the default setting when ability to allocate very
|
|
large blocks of physically contiguous memory is required.
|
|
|
|
Don't change if unsure.
|
|
|
|
endmenu
|
|
|
|
menu "Power management options"
|
|
|
|
config ARCH_HIBERNATION_POSSIBLE
|
|
def_bool y
|
|
|
|
source "kernel/power/Kconfig"
|
|
|
|
endmenu
|