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e65e175b07
Now that we have a subsystem for compute accelerators, move the habanalabs driver to it. This patch only moves the files and fixes the Makefiles. Future patches will change the existing code to register to the accel subsystem and expose the accel device char files instead of the habanalabs device char files. Update the MAINTAINERS file to reflect this change. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
161 lines
6.3 KiB
C
161 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2020-2022 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GAUDI2_MASKS_H_
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#define GAUDI2_MASKS_H_
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#include "../include/gaudi2/asic_reg/gaudi2_regs.h"
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/* Useful masks for bits in various registers */
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#define QMAN_GLBL_ERR_CFG_MSG_EN_MASK \
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((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
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#define QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK \
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((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT))
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#define QMAN_GLBL_ERR_CFG1_MSG_EN_MASK \
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(0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT)
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#define QMAN_GLBL_ERR_CFG1_STOP_ON_ERR_EN_MASK \
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((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT))
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#define QM_PQC_LBW_WDATA \
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((1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT) | \
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(1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT))
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#define QMAN_MAKE_TRUSTED \
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((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))
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#define QMAN_MAKE_TRUSTED_TEST_MODE \
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((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
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(0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \
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(0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))
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#define QMAN_ENABLE \
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((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
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#define PDMA0_QMAN_ENABLE \
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((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
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#define PDMA1_QMAN_ENABLE \
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((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
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(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \
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(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
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/* QM_IDLE_MASK is valid for all engines QM idle check */
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#define QM_IDLE_MASK (DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
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DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
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DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK)
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#define QM_ARC_IDLE_MASK DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK
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#define MME_ARCH_IDLE_MASK \
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(DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK | \
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DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK | \
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DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK | \
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DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK | \
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DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK | \
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DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK)
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#define TPC_IDLE_MASK (DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \
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DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \
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DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \
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DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \
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DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \
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DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK)
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#define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
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/* CGM_IDLE_MASK is valid for all engines CGM idle check */
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#define CGM_IDLE_MASK DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK
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#define QM_GLBL_CFG1_PQF_STOP PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK
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#define QM_GLBL_CFG1_CQF_STOP PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK
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#define QM_GLBL_CFG1_CP_STOP PDMA0_QM_GLBL_CFG1_CP_STOP_MASK
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#define QM_GLBL_CFG1_PQF_FLUSH PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK
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#define QM_GLBL_CFG1_CQF_FLUSH PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK
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#define QM_GLBL_CFG1_CP_FLUSH PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK
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#define QM_GLBL_CFG2_ARC_CQF_STOP PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK
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#define QM_GLBL_CFG2_ARC_CQF_FLUSH PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK
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#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
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#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
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#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
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#define QM_ARB_ERR_MSG_EN_MASK (\
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QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\
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QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\
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QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)
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#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
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#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2
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#define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK GENMASK(1, 0)
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#define MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK BIT(2)
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#define MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK BIT(3)
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#define MME_ACC_INTR_MASK_AP_SRC_NAN_MASK BIT(4)
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#define MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK BIT(5)
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#define MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK BIT(6)
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#define SM_CQ_L2H_MASK_VAL 0xFFFFFFFFFC000000ull
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#define SM_CQ_L2H_CMPR_VAL 0x1000007FFC000000ull
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#define SM_CQ_L2H_LOW_MASK GENMASK(31, 20)
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#define SM_CQ_L2H_LOW_SHIFT 20
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#define MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK \
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REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE)
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#define STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK \
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REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE)
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#define AXUSER_HB_SEC_ASID_MASK 0x3FF
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#define AXUSER_HB_SEC_MMBP_MASK 0x400
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#define MMUBP_ASID_MASK (AXUSER_HB_SEC_ASID_MASK | AXUSER_HB_SEC_MMBP_MASK)
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#define ROT_MSS_HALT_WBC_MASK BIT(0)
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#define ROT_MSS_HALT_RSB_MASK BIT(1)
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#define ROT_MSS_HALT_MRSB_MASK BIT(2)
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#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT 0
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#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK 0x1
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#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_SHIFT 15
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#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK 0x8000
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_SHIFT 0
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK 0x1
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_SHIFT 1
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK 0x2
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_SHIFT 2
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK 0x4
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_SHIFT 3
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_MASK 0x8
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_SHIFT 4
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_MASK 0x10
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_SHIFT 5
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#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_MASK 0x20
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#endif /* GAUDI2_MASKS_H_ */
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