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c35ba0ac48
Split the PORT and CAPs macro definitions into a separate file to facilitate sharing with other files without the need to include the entire xhci.h. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240124152525.3910311-2-Frank.Li@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
86 lines
3.5 KiB
C
86 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* hc_capbase bitmasks */
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/* bits 7:0 - how long is the Capabilities register */
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#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
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/* bits 31:16 */
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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/* HCSPARAMS1 - hcs_params1 - bitmasks */
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/* bits 0:7, Max Device Slots */
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#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
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#define HCS_SLOTS_MASK 0xff
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/* bits 8:18, Max Interrupters */
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#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
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/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
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#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
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/* HCSPARAMS2 - hcs_params2 - bitmasks */
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/* bits 0:3, frames or uframes that SW needs to queue transactions
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* ahead of the HW to meet periodic deadlines */
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#define HCS_IST(p) (((p) >> 0) & 0xf)
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/* bits 4:7, max number of Event Ring segments */
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#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
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/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
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/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
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/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
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#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
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/* HCSPARAMS3 - hcs_params3 - bitmasks */
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/* bits 0:7, Max U1 to U0 latency for the roothub ports */
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#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
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/* bits 16:31, Max U2 to U0 latency for the roothub ports */
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#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
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/* HCCPARAMS - hcc_params - bitmasks */
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/* true: HC can use 64-bit address pointers */
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#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
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/* true: HC can do bandwidth negotiation */
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#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
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/* true: HC uses 64-byte Device Context structures
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* FIXME 64-byte context structures aren't supported yet.
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*/
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#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
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/* true: HC has port power switches */
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#define HCC_PPC(p) ((p) & (1 << 3))
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/* true: HC has port indicators */
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#define HCS_INDICATOR(p) ((p) & (1 << 4))
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/* true: HC has Light HC Reset Capability */
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#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
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/* true: HC supports latency tolerance messaging */
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#define HCC_LTC(p) ((p) & (1 << 6))
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/* true: no secondary Stream ID Support */
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#define HCC_NSS(p) ((p) & (1 << 7))
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/* true: HC supports Stopped - Short Packet */
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#define HCC_SPC(p) ((p) & (1 << 9))
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/* true: HC has Contiguous Frame ID Capability */
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#define HCC_CFC(p) ((p) & (1 << 11))
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/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
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#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
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/* Extended Capabilities pointer from PCI base - section 5.3.6 */
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#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
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#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
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/* db_off bitmask - bits 0:1 reserved */
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#define DBOFF_MASK (~0x3)
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/* run_regs_off bitmask - bits 0:4 reserved */
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#define RTSOFF_MASK (~0x1f)
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/* HCCPARAMS2 - hcc_params2 - bitmasks */
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/* true: HC supports U3 entry Capability */
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#define HCC2_U3C(p) ((p) & (1 << 0))
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/* true: HC supports Configure endpoint command Max exit latency too large */
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#define HCC2_CMC(p) ((p) & (1 << 1))
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/* true: HC supports Force Save context Capability */
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#define HCC2_FSC(p) ((p) & (1 << 2))
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/* true: HC supports Compliance Transition Capability */
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#define HCC2_CTC(p) ((p) & (1 << 3))
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/* true: HC support Large ESIT payload Capability > 48k */
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#define HCC2_LEC(p) ((p) & (1 << 4))
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/* true: HC support Configuration Information Capability */
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#define HCC2_CIC(p) ((p) & (1 << 5))
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/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
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#define HCC2_ETC(p) ((p) & (1 << 6))
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