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1cd95ab85d
and turn the exception handlers into simply returning 0, which simplifies the hell out of things in csum_partial.S Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
755 lines
16 KiB
ArmAsm
755 lines
16 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Quick'n'dirty IP checksum ...
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*
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* Copyright (C) 1998, 1999 Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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* Copyright (C) 2014 Imagination Technologies Ltd.
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*/
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#include <linux/errno.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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#include <asm/regdef.h>
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#ifdef CONFIG_64BIT
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/*
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* As we are sharing code base with the mips32 tree (which use the o32 ABI
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* register definitions). We need to redefine the register definitions from
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* the n64 ABI register naming to the o32 ABI register naming.
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*/
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#undef t0
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#undef t1
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#undef t2
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#undef t3
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#define t0 $8
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define USE_DOUBLE
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#endif
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#ifdef USE_DOUBLE
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#define LOAD ld
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#define LOAD32 lwu
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#define ADD daddu
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#define NBYTES 8
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#else
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#define LOAD lw
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#define LOAD32 lw
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#define ADD addu
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#define NBYTES 4
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#endif /* USE_DOUBLE */
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#define UNIT(unit) ((unit)*NBYTES)
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#define ADDC(sum,reg) \
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.set push; \
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.set noat; \
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ADD sum, reg; \
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sltu v1, sum, reg; \
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ADD sum, v1; \
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.set pop
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#define ADDC32(sum,reg) \
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.set push; \
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.set noat; \
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addu sum, reg; \
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sltu v1, sum, reg; \
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addu sum, v1; \
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.set pop
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#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
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LOAD _t0, (offset + UNIT(0))(src); \
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LOAD _t1, (offset + UNIT(1))(src); \
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LOAD _t2, (offset + UNIT(2))(src); \
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LOAD _t3, (offset + UNIT(3))(src); \
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ADDC(_t0, _t1); \
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ADDC(_t2, _t3); \
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ADDC(sum, _t0); \
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ADDC(sum, _t2)
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#ifdef USE_DOUBLE
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#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \
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CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)
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#else
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#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \
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CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3); \
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CSUM_BIGCHUNK1(src, offset + 0x10, sum, _t0, _t1, _t2, _t3)
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#endif
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/*
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* a0: source address
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* a1: length of the area to checksum
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* a2: partial checksum
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*/
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#define src a0
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#define sum v0
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.text
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.set noreorder
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.align 5
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LEAF(csum_partial)
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EXPORT_SYMBOL(csum_partial)
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move sum, zero
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move t7, zero
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sltiu t8, a1, 0x8
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bnez t8, .Lsmall_csumcpy /* < 8 bytes to copy */
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move t2, a1
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andi t7, src, 0x1 /* odd buffer? */
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.Lhword_align:
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beqz t7, .Lword_align
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andi t8, src, 0x2
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lbu t0, (src)
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LONG_SUBU a1, a1, 0x1
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#ifdef __MIPSEL__
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sll t0, t0, 8
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#endif
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ADDC(sum, t0)
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PTR_ADDU src, src, 0x1
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andi t8, src, 0x2
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.Lword_align:
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beqz t8, .Ldword_align
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sltiu t8, a1, 56
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lhu t0, (src)
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LONG_SUBU a1, a1, 0x2
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ADDC(sum, t0)
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sltiu t8, a1, 56
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PTR_ADDU src, src, 0x2
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.Ldword_align:
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bnez t8, .Ldo_end_words
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move t8, a1
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andi t8, src, 0x4
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beqz t8, .Lqword_align
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andi t8, src, 0x8
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LOAD32 t0, 0x00(src)
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LONG_SUBU a1, a1, 0x4
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ADDC(sum, t0)
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PTR_ADDU src, src, 0x4
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andi t8, src, 0x8
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.Lqword_align:
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beqz t8, .Loword_align
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andi t8, src, 0x10
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#ifdef USE_DOUBLE
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ld t0, 0x00(src)
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LONG_SUBU a1, a1, 0x8
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ADDC(sum, t0)
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#else
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lw t0, 0x00(src)
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lw t1, 0x04(src)
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LONG_SUBU a1, a1, 0x8
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ADDC(sum, t0)
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ADDC(sum, t1)
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#endif
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PTR_ADDU src, src, 0x8
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andi t8, src, 0x10
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.Loword_align:
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beqz t8, .Lbegin_movement
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LONG_SRL t8, a1, 0x7
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#ifdef USE_DOUBLE
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ld t0, 0x00(src)
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ld t1, 0x08(src)
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ADDC(sum, t0)
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ADDC(sum, t1)
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#else
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CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
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#endif
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LONG_SUBU a1, a1, 0x10
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PTR_ADDU src, src, 0x10
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LONG_SRL t8, a1, 0x7
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.Lbegin_movement:
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beqz t8, 1f
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andi t2, a1, 0x40
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.Lmove_128bytes:
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CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
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LONG_SUBU t8, t8, 0x01
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.set reorder /* DADDI_WAR */
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PTR_ADDU src, src, 0x80
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bnez t8, .Lmove_128bytes
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.set noreorder
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1:
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beqz t2, 1f
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andi t2, a1, 0x20
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.Lmove_64bytes:
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CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
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PTR_ADDU src, src, 0x40
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1:
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beqz t2, .Ldo_end_words
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andi t8, a1, 0x1c
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.Lmove_32bytes:
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CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
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andi t8, a1, 0x1c
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PTR_ADDU src, src, 0x20
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.Ldo_end_words:
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beqz t8, .Lsmall_csumcpy
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andi t2, a1, 0x3
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LONG_SRL t8, t8, 0x2
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.Lend_words:
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LOAD32 t0, (src)
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LONG_SUBU t8, t8, 0x1
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ADDC(sum, t0)
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.set reorder /* DADDI_WAR */
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PTR_ADDU src, src, 0x4
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bnez t8, .Lend_words
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.set noreorder
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/* unknown src alignment and < 8 bytes to go */
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.Lsmall_csumcpy:
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move a1, t2
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andi t0, a1, 4
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beqz t0, 1f
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andi t0, a1, 2
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/* Still a full word to go */
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ulw t1, (src)
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PTR_ADDIU src, 4
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#ifdef USE_DOUBLE
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dsll t1, t1, 32 /* clear lower 32bit */
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#endif
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ADDC(sum, t1)
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1: move t1, zero
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beqz t0, 1f
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andi t0, a1, 1
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/* Still a halfword to go */
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ulhu t1, (src)
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PTR_ADDIU src, 2
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1: beqz t0, 1f
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sll t1, t1, 16
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lbu t2, (src)
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nop
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#ifdef __MIPSEB__
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sll t2, t2, 8
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#endif
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or t1, t2
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1: ADDC(sum, t1)
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/* fold checksum */
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#ifdef USE_DOUBLE
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dsll32 v1, sum, 0
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daddu sum, v1
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sltu v1, sum, v1
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dsra32 sum, sum, 0
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addu sum, v1
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#endif
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/* odd buffer alignment? */
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
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defined(CONFIG_CPU_LOONGSON64)
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.set push
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.set arch=mips32r2
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wsbh v1, sum
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movn sum, v1, t7
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.set pop
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#else
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beqz t7, 1f /* odd buffer alignment? */
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lui v1, 0x00ff
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addu v1, 0x00ff
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and t0, sum, v1
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sll t0, t0, 8
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srl sum, sum, 8
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and sum, sum, v1
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or sum, sum, t0
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1:
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#endif
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.set reorder
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/* Add the passed partial csum. */
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ADDC32(sum, a2)
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jr ra
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.set noreorder
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END(csum_partial)
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/*
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* checksum and copy routines based on memcpy.S
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*
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* csum_partial_copy_nocheck(src, dst, len)
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* __csum_partial_copy_kernel(src, dst, len)
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*
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* See "Spec" in memcpy.S for details. Unlike __copy_user, all
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* function in this file use the standard calling convention.
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*/
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#define src a0
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#define dst a1
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#define len a2
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#define sum v0
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#define odd t8
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/*
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* All exception handlers simply return 0.
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*/
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/* Instruction type */
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#define LD_INSN 1
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#define ST_INSN 2
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#define LEGACY_MODE 1
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#define EVA_MODE 2
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#define USEROP 1
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#define KERNELOP 2
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/*
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* Wrapper to add an entry in the exception table
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* in case the insn causes a memory exception.
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* Arguments:
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* insn : Load/store instruction
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* type : Instruction type
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* reg : Register
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* addr : Address
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* handler : Exception handler
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*/
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#define EXC(insn, type, reg, addr) \
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.if \mode == LEGACY_MODE; \
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9: insn reg, addr; \
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.section __ex_table,"a"; \
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PTR 9b, .L_exc; \
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.previous; \
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/* This is enabled in EVA mode */ \
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.else; \
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/* If loading from user or storing to user */ \
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.if ((\from == USEROP) && (type == LD_INSN)) || \
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((\to == USEROP) && (type == ST_INSN)); \
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9: __BUILD_EVA_INSN(insn##e, reg, addr); \
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.section __ex_table,"a"; \
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PTR 9b, .L_exc; \
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.previous; \
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.else; \
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/* EVA without exception */ \
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insn reg, addr; \
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.endif; \
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.endif
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#undef LOAD
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#ifdef USE_DOUBLE
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#define LOADK ld /* No exception */
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#define LOAD(reg, addr) EXC(ld, LD_INSN, reg, addr)
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#define LOADBU(reg, addr) EXC(lbu, LD_INSN, reg, addr)
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#define LOADL(reg, addr) EXC(ldl, LD_INSN, reg, addr)
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#define LOADR(reg, addr) EXC(ldr, LD_INSN, reg, addr)
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#define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
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#define STOREL(reg, addr) EXC(sdl, ST_INSN, reg, addr)
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#define STORER(reg, addr) EXC(sdr, ST_INSN, reg, addr)
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#define STORE(reg, addr) EXC(sd, ST_INSN, reg, addr)
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#define ADD daddu
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#define SUB dsubu
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#define SRL dsrl
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#define SLL dsll
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#define SLLV dsllv
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#define SRLV dsrlv
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#define NBYTES 8
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#define LOG_NBYTES 3
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#else
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#define LOADK lw /* No exception */
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#define LOAD(reg, addr) EXC(lw, LD_INSN, reg, addr)
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#define LOADBU(reg, addr) EXC(lbu, LD_INSN, reg, addr)
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#define LOADL(reg, addr) EXC(lwl, LD_INSN, reg, addr)
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#define LOADR(reg, addr) EXC(lwr, LD_INSN, reg, addr)
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#define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
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#define STOREL(reg, addr) EXC(swl, ST_INSN, reg, addr)
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#define STORER(reg, addr) EXC(swr, ST_INSN, reg, addr)
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#define STORE(reg, addr) EXC(sw, ST_INSN, reg, addr)
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#define ADD addu
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#define SUB subu
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#define SRL srl
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#define SLL sll
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#define SLLV sllv
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#define SRLV srlv
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#define NBYTES 4
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#define LOG_NBYTES 2
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#endif /* USE_DOUBLE */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define LDFIRST LOADR
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#define LDREST LOADL
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#define STFIRST STORER
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#define STREST STOREL
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#define SHIFT_DISCARD SLLV
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#define SHIFT_DISCARD_REVERT SRLV
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#else
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#define LDFIRST LOADL
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#define LDREST LOADR
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#define STFIRST STOREL
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#define STREST STORER
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#define SHIFT_DISCARD SRLV
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#define SHIFT_DISCARD_REVERT SLLV
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#endif
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#define FIRST(unit) ((unit)*NBYTES)
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#define REST(unit) (FIRST(unit)+NBYTES-1)
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#define ADDRMASK (NBYTES-1)
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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.set noat
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#else
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.set at=v1
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#endif
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.macro __BUILD_CSUM_PARTIAL_COPY_USER mode, from, to
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li sum, -1
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move odd, zero
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/*
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* Note: dst & src may be unaligned, len may be 0
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* Temps
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*/
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/*
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* The "issue break"s below are very approximate.
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* Issue delays for dcache fills will perturb the schedule, as will
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* load queue full replay traps, etc.
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*
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* If len < NBYTES use byte operations.
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*/
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sltu t2, len, NBYTES
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and t1, dst, ADDRMASK
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bnez t2, .Lcopy_bytes_checklen\@
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and t0, src, ADDRMASK
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andi odd, dst, 0x1 /* odd buffer? */
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bnez t1, .Ldst_unaligned\@
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nop
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bnez t0, .Lsrc_unaligned_dst_aligned\@
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/*
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* use delay slot for fall-through
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* src and dst are aligned; need to compute rem
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*/
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.Lboth_aligned\@:
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SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
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beqz t0, .Lcleanup_both_aligned\@ # len < 8*NBYTES
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nop
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SUB len, 8*NBYTES # subtract here for bgez loop
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.align 4
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1:
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LOAD(t0, UNIT(0)(src))
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LOAD(t1, UNIT(1)(src))
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LOAD(t2, UNIT(2)(src))
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LOAD(t3, UNIT(3)(src))
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LOAD(t4, UNIT(4)(src))
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LOAD(t5, UNIT(5)(src))
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LOAD(t6, UNIT(6)(src))
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LOAD(t7, UNIT(7)(src))
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SUB len, len, 8*NBYTES
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ADD src, src, 8*NBYTES
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STORE(t0, UNIT(0)(dst))
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ADDC(t0, t1)
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STORE(t1, UNIT(1)(dst))
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ADDC(sum, t0)
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STORE(t2, UNIT(2)(dst))
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ADDC(t2, t3)
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STORE(t3, UNIT(3)(dst))
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ADDC(sum, t2)
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STORE(t4, UNIT(4)(dst))
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ADDC(t4, t5)
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STORE(t5, UNIT(5)(dst))
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ADDC(sum, t4)
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STORE(t6, UNIT(6)(dst))
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ADDC(t6, t7)
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STORE(t7, UNIT(7)(dst))
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ADDC(sum, t6)
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.set reorder /* DADDI_WAR */
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ADD dst, dst, 8*NBYTES
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bgez len, 1b
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.set noreorder
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ADD len, 8*NBYTES # revert len (see above)
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/*
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* len == the number of bytes left to copy < 8*NBYTES
|
|
*/
|
|
.Lcleanup_both_aligned\@:
|
|
#define rem t7
|
|
beqz len, .Ldone\@
|
|
sltu t0, len, 4*NBYTES
|
|
bnez t0, .Lless_than_4units\@
|
|
and rem, len, (NBYTES-1) # rem = len % NBYTES
|
|
/*
|
|
* len >= 4*NBYTES
|
|
*/
|
|
LOAD(t0, UNIT(0)(src))
|
|
LOAD(t1, UNIT(1)(src))
|
|
LOAD(t2, UNIT(2)(src))
|
|
LOAD(t3, UNIT(3)(src))
|
|
SUB len, len, 4*NBYTES
|
|
ADD src, src, 4*NBYTES
|
|
STORE(t0, UNIT(0)(dst))
|
|
ADDC(t0, t1)
|
|
STORE(t1, UNIT(1)(dst))
|
|
ADDC(sum, t0)
|
|
STORE(t2, UNIT(2)(dst))
|
|
ADDC(t2, t3)
|
|
STORE(t3, UNIT(3)(dst))
|
|
ADDC(sum, t2)
|
|
.set reorder /* DADDI_WAR */
|
|
ADD dst, dst, 4*NBYTES
|
|
beqz len, .Ldone\@
|
|
.set noreorder
|
|
.Lless_than_4units\@:
|
|
/*
|
|
* rem = len % NBYTES
|
|
*/
|
|
beq rem, len, .Lcopy_bytes\@
|
|
nop
|
|
1:
|
|
LOAD(t0, 0(src))
|
|
ADD src, src, NBYTES
|
|
SUB len, len, NBYTES
|
|
STORE(t0, 0(dst))
|
|
ADDC(sum, t0)
|
|
.set reorder /* DADDI_WAR */
|
|
ADD dst, dst, NBYTES
|
|
bne rem, len, 1b
|
|
.set noreorder
|
|
|
|
/*
|
|
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
|
|
* A loop would do only a byte at a time with possible branch
|
|
* mispredicts. Can't do an explicit LOAD dst,mask,or,STORE
|
|
* because can't assume read-access to dst. Instead, use
|
|
* STREST dst, which doesn't require read access to dst.
|
|
*
|
|
* This code should perform better than a simple loop on modern,
|
|
* wide-issue mips processors because the code has fewer branches and
|
|
* more instruction-level parallelism.
|
|
*/
|
|
#define bits t2
|
|
beqz len, .Ldone\@
|
|
ADD t1, dst, len # t1 is just past last byte of dst
|
|
li bits, 8*NBYTES
|
|
SLL rem, len, 3 # rem = number of bits to keep
|
|
LOAD(t0, 0(src))
|
|
SUB bits, bits, rem # bits = number of bits to discard
|
|
SHIFT_DISCARD t0, t0, bits
|
|
STREST(t0, -1(t1))
|
|
SHIFT_DISCARD_REVERT t0, t0, bits
|
|
.set reorder
|
|
ADDC(sum, t0)
|
|
b .Ldone\@
|
|
.set noreorder
|
|
.Ldst_unaligned\@:
|
|
/*
|
|
* dst is unaligned
|
|
* t0 = src & ADDRMASK
|
|
* t1 = dst & ADDRMASK; T1 > 0
|
|
* len >= NBYTES
|
|
*
|
|
* Copy enough bytes to align dst
|
|
* Set match = (src and dst have same alignment)
|
|
*/
|
|
#define match rem
|
|
LDFIRST(t3, FIRST(0)(src))
|
|
ADD t2, zero, NBYTES
|
|
LDREST(t3, REST(0)(src))
|
|
SUB t2, t2, t1 # t2 = number of bytes copied
|
|
xor match, t0, t1
|
|
STFIRST(t3, FIRST(0)(dst))
|
|
SLL t4, t1, 3 # t4 = number of bits to discard
|
|
SHIFT_DISCARD t3, t3, t4
|
|
/* no SHIFT_DISCARD_REVERT to handle odd buffer properly */
|
|
ADDC(sum, t3)
|
|
beq len, t2, .Ldone\@
|
|
SUB len, len, t2
|
|
ADD dst, dst, t2
|
|
beqz match, .Lboth_aligned\@
|
|
ADD src, src, t2
|
|
|
|
.Lsrc_unaligned_dst_aligned\@:
|
|
SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
|
|
beqz t0, .Lcleanup_src_unaligned\@
|
|
and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
|
|
1:
|
|
/*
|
|
* Avoid consecutive LD*'s to the same register since some mips
|
|
* implementations can't issue them in the same cycle.
|
|
* It's OK to load FIRST(N+1) before REST(N) because the two addresses
|
|
* are to the same unit (unless src is aligned, but it's not).
|
|
*/
|
|
LDFIRST(t0, FIRST(0)(src))
|
|
LDFIRST(t1, FIRST(1)(src))
|
|
SUB len, len, 4*NBYTES
|
|
LDREST(t0, REST(0)(src))
|
|
LDREST(t1, REST(1)(src))
|
|
LDFIRST(t2, FIRST(2)(src))
|
|
LDFIRST(t3, FIRST(3)(src))
|
|
LDREST(t2, REST(2)(src))
|
|
LDREST(t3, REST(3)(src))
|
|
ADD src, src, 4*NBYTES
|
|
#ifdef CONFIG_CPU_SB1
|
|
nop # improves slotting
|
|
#endif
|
|
STORE(t0, UNIT(0)(dst))
|
|
ADDC(t0, t1)
|
|
STORE(t1, UNIT(1)(dst))
|
|
ADDC(sum, t0)
|
|
STORE(t2, UNIT(2)(dst))
|
|
ADDC(t2, t3)
|
|
STORE(t3, UNIT(3)(dst))
|
|
ADDC(sum, t2)
|
|
.set reorder /* DADDI_WAR */
|
|
ADD dst, dst, 4*NBYTES
|
|
bne len, rem, 1b
|
|
.set noreorder
|
|
|
|
.Lcleanup_src_unaligned\@:
|
|
beqz len, .Ldone\@
|
|
and rem, len, NBYTES-1 # rem = len % NBYTES
|
|
beq rem, len, .Lcopy_bytes\@
|
|
nop
|
|
1:
|
|
LDFIRST(t0, FIRST(0)(src))
|
|
LDREST(t0, REST(0)(src))
|
|
ADD src, src, NBYTES
|
|
SUB len, len, NBYTES
|
|
STORE(t0, 0(dst))
|
|
ADDC(sum, t0)
|
|
.set reorder /* DADDI_WAR */
|
|
ADD dst, dst, NBYTES
|
|
bne len, rem, 1b
|
|
.set noreorder
|
|
|
|
.Lcopy_bytes_checklen\@:
|
|
beqz len, .Ldone\@
|
|
nop
|
|
.Lcopy_bytes\@:
|
|
/* 0 < len < NBYTES */
|
|
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
|
#define SHIFT_START 0
|
|
#define SHIFT_INC 8
|
|
#else
|
|
#define SHIFT_START 8*(NBYTES-1)
|
|
#define SHIFT_INC -8
|
|
#endif
|
|
move t2, zero # partial word
|
|
li t3, SHIFT_START # shift
|
|
#define COPY_BYTE(N) \
|
|
LOADBU(t0, N(src)); \
|
|
SUB len, len, 1; \
|
|
STOREB(t0, N(dst)); \
|
|
SLLV t0, t0, t3; \
|
|
addu t3, SHIFT_INC; \
|
|
beqz len, .Lcopy_bytes_done\@; \
|
|
or t2, t0
|
|
|
|
COPY_BYTE(0)
|
|
COPY_BYTE(1)
|
|
#ifdef USE_DOUBLE
|
|
COPY_BYTE(2)
|
|
COPY_BYTE(3)
|
|
COPY_BYTE(4)
|
|
COPY_BYTE(5)
|
|
#endif
|
|
LOADBU(t0, NBYTES-2(src))
|
|
SUB len, len, 1
|
|
STOREB(t0, NBYTES-2(dst))
|
|
SLLV t0, t0, t3
|
|
or t2, t0
|
|
.Lcopy_bytes_done\@:
|
|
ADDC(sum, t2)
|
|
.Ldone\@:
|
|
/* fold checksum */
|
|
.set push
|
|
.set noat
|
|
#ifdef USE_DOUBLE
|
|
dsll32 v1, sum, 0
|
|
daddu sum, v1
|
|
sltu v1, sum, v1
|
|
dsra32 sum, sum, 0
|
|
addu sum, v1
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
|
|
defined(CONFIG_CPU_LOONGSON64)
|
|
.set push
|
|
.set arch=mips32r2
|
|
wsbh v1, sum
|
|
movn sum, v1, odd
|
|
.set pop
|
|
#else
|
|
beqz odd, 1f /* odd buffer alignment? */
|
|
lui v1, 0x00ff
|
|
addu v1, 0x00ff
|
|
and t0, sum, v1
|
|
sll t0, t0, 8
|
|
srl sum, sum, 8
|
|
and sum, sum, v1
|
|
or sum, sum, t0
|
|
1:
|
|
#endif
|
|
.set pop
|
|
.set reorder
|
|
jr ra
|
|
.set noreorder
|
|
.endm
|
|
|
|
.set noreorder
|
|
.L_exc:
|
|
jr ra
|
|
li v0, 0
|
|
|
|
FEXPORT(__csum_partial_copy_nocheck)
|
|
EXPORT_SYMBOL(__csum_partial_copy_nocheck)
|
|
#ifndef CONFIG_EVA
|
|
FEXPORT(__csum_partial_copy_to_user)
|
|
EXPORT_SYMBOL(__csum_partial_copy_to_user)
|
|
FEXPORT(__csum_partial_copy_from_user)
|
|
EXPORT_SYMBOL(__csum_partial_copy_from_user)
|
|
#endif
|
|
__BUILD_CSUM_PARTIAL_COPY_USER LEGACY_MODE USEROP USEROP
|
|
|
|
#ifdef CONFIG_EVA
|
|
LEAF(__csum_partial_copy_to_user)
|
|
__BUILD_CSUM_PARTIAL_COPY_USER EVA_MODE KERNELOP USEROP
|
|
END(__csum_partial_copy_to_user)
|
|
|
|
LEAF(__csum_partial_copy_from_user)
|
|
__BUILD_CSUM_PARTIAL_COPY_USER EVA_MODE USEROP KERNELOP
|
|
END(__csum_partial_copy_from_user)
|
|
#endif
|