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linux/include/asm-arm/arch-orion5x
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Ke Wei 1219715de7 [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define 
Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.

This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:01 +02:00
..
debug-macro.S Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
dma.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
entry-macro.S Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
gpio.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
hardware.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
io.h [ARM] Orion: nuke orion5x_{read,write} 2008-06-22 22:44:57 +02:00
irqs.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
memory.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
orion5x.h [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define 2008-06-22 22:45:01 +02:00
system.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
timex.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00
uncompress.h [ARM] Orion: use linux/serial_reg.h for Orion uncompress.h 2008-06-22 22:44:56 +02:00
vmalloc.h Orion: orion -> orion5x rename 2008-03-27 14:51:41 -04:00